SAM9G25 Atmel Corporation, SAM9G25 Datasheet - Page 36
SAM9G25
Manufacturer Part Number
SAM9G25
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G25.pdf
(1147 pages)
5.SAM9G25.pdf
(53 pages)
Specifications of SAM9G25
Flash (kbytes)
0 Kbytes
Pin Count
247
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
105
Ext Interrupts
105
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
3
Uart
7
Lin
4
Ssc
1
Ethernet
1
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
Yes
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
NO
External Bus Interface
1
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G25 PDF datasheet #4
- SAM9G25 PDF datasheet #5
- Current page: 36 of 248
- Download datasheet (2Mb)
Programmer’s Model
2-8
ID Code Register c0
This is a read-only register that returns the 32-bit device ID code.
You can access the ID Code Register by reading CP15 register c0 with the Opcode_2
field set to any value other than 1 or 2. For example:
The contents of the ID Code Register are shown in Table 2-5.
Cache Type Register c0
This is a read-only register that contains information about the size and architecture of
the Instruction Cache (ICache) and Data Cache (DCache) enabling operating systems
to establish how to perform such operations as cache cleaning and lockdown.
You can access the cache type register by reading CP15 register c0 with the Opcode_2
field set to 1. For example:
The format of the Cache Type Register is shown in Figure 2-2 on page 2-9.
Copyright © 2001-2003 ARM Limited. All rights reserved.
Register bits
[31:24]
[23:20]
[19:16]
[15:4]
[3:0]
a. The revision value can be in the range 0x0 to 0x5, depending on the
layout revision you are using..
Function
ASCII code of implementer trademark
Variant
Architecture (ARMv5TEJ)
Part number
Revision
Table 2-5 Register 0, ID code
ARM DDI0198D
Value
a
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