SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 112
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SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 112 of 290
- Download datasheet (5Mb)
Interrupts
5-4
takes the FIQ exception in a later cycle, even if the nFIQ input is subsequently
deasserted.
There are several approaches that you can adopt to ensure that interrupts are not enabled
too early on the ARM9E-S. The best approach is highly dependent on the overall
system, and can be a combination of hardware and software.
nFIQ or nIRQ) typically does not take effect until after the Memory stage of that
instruction. The instruction that re-enables interrupts on the ARM9E-S can cause the
ARM9E-S to be sensitive to interrupts as early as the Execute stage of that instruction.
For example, consider the following instruction sequence:
STR r0, [r1] ;Write to interrupt controller, clearing interrupt
SUBS pc, r14, #4 ;Return from interrupt routine
The execution of this code sequence is illustrated in Figure 5-1.
In Figure 5-1, the
nFIQ input until cycle 4. The
interrupts during cycle 3.
Because of this timing relationship, the ARM9E-S retakes the FIQ exception in this
example.
The FIQDIS (and similarly IRQDIS) output from the ARM9E-S indicates when the
ARM9E-S is sensitive to the state of the nFIQ (nIRQ) input (0 for sensitive, 1 for
insensitive). If nFIQ is asserted in the same cycle that FIQDIS is LOW, the ARM9E-S
STR r0, [r1]
SUBS pc, r14, #4
Copyright © 2000 ARM Limited. All rights reserved.
STR
to the interrupt controller does not cause the deassertion of the
SUBS
instruction causes the ARM9E-S to be sensitive to
Figure 5-1 Retaking the FIQ exception
ARM DDI 0165B
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