SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 248
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 248 of 290
- Download datasheet (5Mb)
Debug in depth
C.4.3
C.4.4
C-8
SCAN_N (0010)
INTEST (1100)
The SCAN_N instruction connects the scan path select register between DBGTDI and
DBGTDO:
•
•
•
•
The scan path select register is 4 bits long in this implementation, although no finite
length is specified.
The INTEST instruction places the selected scan chain in test mode:
•
•
•
•
Single-step operation of the core is possible using the INTEST instruction.
In the CAPTURE-DR state, the fixed value
In the SHIFT-DR state, the ID number of the desired scan path is shifted into the
scan path select register.
In the UPDATE-DR state, the scan register of the selected scan chain is connected
between DBGTDI and DBGTDO, and remains connected until a subsequent
SCAN_N instruction is issued.
On reset, scan chain 0 is selected by default.
The INTEST instruction connects the selected scan chain between DBGTDI and
DBGTDO.
When the INTEST instruction is loaded into the instruction register, all the scan
cells are placed in their test mode of operation. For example, in test mode, input
cells select the output of the scan chain to be applied to the core.
In the CAPTURE-DR state, the value of the data applied from the core logic to
the output scan cells, and the value of the data applied from the system logic to
the input scan cells is captured.
In the SHIFT-DR state, the previously-captured test data is shifted out of the scan
chain via the DBGTDO pin, while new test data is shifted in via the DBGTDI
pin.
Copyright © 2000 ARM Limited. All rights reserved.
1000
is loaded into the register.
ARM DDI 0165B
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