SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 58

• Manufacturer Part Number: SAM9RL64
• Manufacturer: Atmel Corporation

Specifications of SAM9RL64

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 240 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 118
• Ext Interrupts: 118
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 5
• Ssc: 2
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 6
• Adc Resolution (bits): 10
• Adc Speed (ksps): 220
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Programmer’s Model
2.8
2.8.1
2-16
The program status registers
The condition code flags
The ARM9E-S contains a CPSR, and five SPSRs for exception handlers to use. The
program status registers:
•
•
•
The arrangement of bits in the status registers is shown in Figure 2-6.
The unused bits of the status registers might be used in future ARM architectures, and
must not be modified by software. The unused bits of the status registers are readable,
to allow the processor state to be preserved (for example, during process context
switches) and writable, to allow the processor state to be restored. To maintain
compatibility with future ARM processors, and as good practice, you are strongly
advised to use a read-modify-write strategy when changing the CPSR.
The N, Z, C, and V bits are the condition code flags. They can be set by arithmetic and
logical operations, and also by MSR and LDM instructions. The ARM9E-S tests these
flags to determine whether to execute an instruction.
All instructions can execute conditionally on the state of the N, Z, C, and V bits in ARM
state. In Thumb state, only the Branch instruction can be executed conditionally. For
more information about conditional execution, refer to the ARM Architecture Reference
Manual.
hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operating mode.
Note
Copyright © 2000 ARM Limited. All rights reserved.
Sticky overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
Figure 2-6 Program status register
ARM DDI 0165B
Mode bits
State bit
FIQ disable
IRQ disable