SAM9RL64 Atmel Corporation, SAM9RL64 Datasheet - Page 30
SAM9RL64
Manufacturer Part Number
SAM9RL64
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9260.pdf
(290 pages)
3.SAM9261.pdf
(248 pages)
4.SAM9R64.pdf
(903 pages)
5.SAM9R64.pdf
(52 pages)
Specifications of SAM9RL64
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
240 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
118
Ext Interrupts
118
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
5
Ssc
2
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
220
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No / Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- M40800 PDF datasheet
- SAM9260 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9R64 PDF datasheet #4
- SAM9R64 PDF datasheet #5
- Current page: 30 of 290
- Download datasheet (5Mb)
Introduction
1.4.1
1-12
Operation
Move
Arithmetic
ARM instruction set summary
Move
Move NOT
Move SPSR to register
Move CPSR to register
Move register to SPSR
Move register to CPSR
Move immediate to SPSR flags
Move immediate to CPSR flags
Add
Add with carry
Subtract
Subtract with carry
Reverse subtract
Reverse subtract with carry
Multiply
Multiply accumulate
Multiply unsigned long
Multiply unsigned accumulate long
Multiply signed long
Multiply signed accumulate long
Compare
Compare negative
Saturating add
The ARM instruction set summary is given in Table 1-2.
Copyright © 2000 ARM Limited. All rights reserved.
Assembler
MOV{cond}{S} Rd, <Oprnd2>
MVN{cond}{S} Rd, <Oprnd2>
MRS{cond} Rd, SPSR
MRS{cond} Rd, CPSR
MSR{cond} SPSR{field}, Rm
MSR{cond} CPSR{field}, Rm
MSR{cond} SPSR_flg, #32bit_Imm
MSR{cond} CPSR_flg, #32bit_Imm
ADD{cond}{S} Rd, Rn, <Oprnd2>
ADC{cond}{S} Rd, Rn, <Oprnd2>
SUB{cond}{S} Rd, Rn, <Oprnd2>
SBC{cond}{S} Rd, Rn, <Oprnd2>
RSB{cond}{S} Rd, Rn, <Oprnd2>
RSC{cond}{S} Rd, Rn, <Oprnd2>
MUL{cond}{S} Rd, Rm, Rs
MLA{cond}{S} Rd, Rm, Rs, Rn
UMULL{cond}{S} RdLo, RdHi, Rm, Rs
UMLAL{cond}{S} RdLo, RdHi, Rm, Rs
SMULL{cond}{S} RdLo, RdHi, Rm, Rs
SMLAL{cond}{S} RdLo, RdHi, Rm, Rs
CMP{cond} Rd, <Oprnd2>
CMN{cond} Rd, <Oprnd2>
QADD{cond} Rd, Rn, Rs
Table 1-2 ARM instruction set summary
ARM DDI 0165B
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