SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet
SAM3SD8B
Related parts for SAM3SD8B
SAM3SD8B Summary of contents
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Features • Core ® ® – ARM Cortex -M3 revision 2.0 running MHz – Memory Protection Unit (MPU) ® – Thumb -2 instruction set • Pin-to-pin compatible with AT91SAM7S legacy products (64-pin versions), SAM3S4/2/1 products • ...
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... Full Modem support on USART1. 2. One channel is reserved for internal temperature sensor. ® SAM3S8C SAM3SD8B 512 Kbytes 512 Kbytes 64 Kbytes 64 Kbytes LQFP100 LQFP64 BGA100 QFN64 79 47 (2) (2) 11 channels 2 channels 2 channels ...
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Block Diagram Figure 2-1. SAM3S8/SD8 100-pin version Block Diagram System Controller TST PCK0-PCK2 PLLA PLLB RC Osc 12/8/4 MHz XIN 3-20 MHz XOUT SUPC XIN32 Osc 32 kHz XOUT32 RC 32 kHz ERASE 8 GPBREG VDDIO VDDCORE RTT VDDPLL ...
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Figure 2-2. SAM3S8/SD8 64-pin version Block Diagram System Controller TST PCK0-PCK2 PLLA PLLB RC Osc 12/8/4 MHz XIN 3-20 MHz XOUT SUPC XIN32 Osc 32 kHz XOUT32 RC 32 kHz ERASE 8 GPBREG VDDIO VDDCORE RTT VDDPLL POR RTCOUT0 RTC ...
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Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function Peripherals I/O Lines and USB transceiver VDDIO Power Supply Voltage Regulator Input, ADC, DAC and VDDIN Analog Comparator Power Supply VDDOUT Voltage Regulator Output VDDPLL Oscillator and ...
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Table 3-1. Signal Description List (Continued) Signal Name Function Flash and NVM Configuration Bits Erase ERASE Command NRST Synchronous Microcontroller Reset TST Test Select URXDx UART Receive Data UTXDx UART Transmit Data PA0 - PA31 Parallel IO Controller A PB0 ...
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Table 3-1. Signal Description List (Continued) Signal Name Function Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx USARTx Serial Clock TXDx USARTx Transmit Data RXDx USARTx Receive Data RTSx USARTx Request To Send CTSx USARTx Clear To Send DTR1 USART1 Data ...
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Table 3-1. Signal Description List (Continued) Signal Name Function TWDx TWIx Two-wire Serial Data TWCKx TWIx Two-wire Serial Clock ADC, DAC and Analog Comparator ADVREF Reference AD0-AD14 Analog Inputs ADTRG ADC Trigger DAC0 - DAC1 Analog output DACTRG DAC Trigger ...
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Package and Pinout SAM3S8/SD8 devices are pin-to-pin compatible with AT91SAM7S legacy products for 64-pin version. Furthermore, SAM3S8/SD8 products have new functionalities referenced in italic in Table 4-1, 4.1 SAM3S8C/8DC Package and Pinout 4.1.1 100-Lead LQFP Package Outline Figure 4-1. ...
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LQFP Pinout Table 4-1. SAM3S8C/SD8C 100-lead LQFP pinout 1 ADVREF 26 2 GND 27 3 PB0/AD4 28 4 PC29/AD13 29 5 PB1/AD5 30 6 PC30/AD14 31 7 PB2/AD6 32 8 PC31 33 9 PB3/AD7 34 10 VDDIN 35 ...
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TFBGA Pinout Table 4-2. SAM3S8C/SD8C 100-ball TFBGA pinout A1 PB1/AD5 A2 PC29 A3 VDDIO A4 PB9/PGMCK/XIN A5 PB8/XOUT C10 A6 PB13/DAC0 A7 DDP/PB11 A8 DDM/PB10 A9 TMS/SWDIO/PB6 A10 JTAGSEL B1 PC30 B2 ADVREF B3 GNDANA B4 PB14/DAC1 B5 ...
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SAM3S8B/D8B Package and Pinout 4.2.1 64-Lead LQFP Package Outline Figure 4-3. 4.2.2 64-lead QFN Package Outline Figure 4-4. SAM3S8/SD8 Summary 12 Orientation of the 64-lead LQFP Package Orientation of the 64-lead QFN Package 64 1 ...
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LQFP and QFN Pinout Table 4-3. 64-pin SAM3S8B/D8B pinout 1 ADVREF 2 GND 3 PB0/AD4 4 PB1/AD5 5 PB2/AD6 6 PB3/AD7 7 VDDIN 8 VDDOUT PA17/PGMD5/ 9 AD0 PA18/PGMD6/ 10 AD1 PA21/PGMD9/ 11 AD8 12 VDDCORE PA19/PGMD7/ 13 ...
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Power Considerations 5.1 Power Supplies The SAM3S8/SD8 has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals. Voltage ranges from 1.62V to 1.95V. • VDDIO pins: Power the Peripherals I/O ...
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Figure 5-1. Note: Figure 5-2. Note: Figure 5-3 Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line at low level (PIO ...
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Figure 5-3. 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency ...
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Supply Monitor alarm • RTC alarm • RTT alarm 5.5.2 Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of ...
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Low Power Mode Summary Table The modes detailed above are the main low-power modes. Each part can be set off sep- arately and wake up sources can be individually configured. of the configurations of the low-power ...
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Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply and the SRAM power supply, if they ...
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Fast Startup The SAM3S8/SD8 allows the processor to restart in a few microseconds while the processor is in wait mode or in sleep mode. A fast start up can occur upon detection of a low level on one of ...
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Input/Output Lines The SAM3S8/SD8 has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be ...
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Table 6-1. System I/O Configuration Pin List. SYSTEM_IO Default function bit number after reset 12 ERASE 10 DDM 11 DDP 7 TCK/SWCLK 6 TMS/SWDIO 5 TDO/TRACESWO 4 TDI - PA7 - PA8 - PB9 - PB8 Notes PB12 ...
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Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3S8/SD8 series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it ...
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Processor and Architecture 7.1 ARM Cortex-M3 Processor • Version 2.0 • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit. • Harvard processor architecture enabling simultaneous instruction fetch with data load/store. • Three-stage pipeline. • Single ...
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Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths are forbidden or ...
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Table 7-4. Instance name SSC HSMCI PIOA TWI1 TWI0 UART1 UART0 USART1 USART0 ADC SPI SSC HSMCI 7.7 Debug and Test Features • Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core ...
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Product Mapping Figure 8-1. SAM3S8/SD8 Product Mapping Code 0x00000000 Boot Memory 0x00400000 Internal Flash 0x00800000 Internal ROM 0x00C00000 Reserved 0x1FFFFFFF External RAM 0x60000000 SMC Chip Select 0 0x61000000 SMC Chip Select 1 0x62000000 SMC Chip Select 2 0x63000000 SMC ...
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Memories 9.1 Embedded Memories 9.1.1 Internal SRAM The SAM3S8 device (512-Kbytes, single bank flash) embeds a total of 64-Kbytes high-speed SRAM. The SAM3SD8 device (512-Kbytes, dual bank flash) embeds a total of 64-Kbytes high-speed SRAM. The SRAM is accessible ...
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Flash Speed The user needs to set the number of wait states depending on the frequency used: For more details, refer to the “AC Characteristics” sub-section of the product “Electrical Characteristics”. 9.1.3.5 Lock Regions Several lock bits are used ...
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The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. 9.1.3.10 SAM-BA Boot The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA ...
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External Memories The SAM3S8/SD8 features one External Bus Interface to provide an interface to a wide range of external memories and to any parallel peripheral. 9.2.1 Static Memory Controller • 16-Mbyte Address Space per Chip Select • 8- bit ...
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Figure 10-1. System Controller Block Diagram VDDIO Zero-Power Power-on Reset Supply Monitor (Backup) WKUP0 - WKUP15 General Purpose Backup Registers SLCK SLCK XIN32 Xtal 32 kHz Oscillator XOUT32 Embedded 32 kHz RC Oscillator Backup Power Supply NRST FSTT0 - FSTT15 ...
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System Controller and Peripherals Mapping Please refer to All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3S8/SD8 embeds three features to monitor, ...
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The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell. The zero-power power-on reset allows the Supply Controller to start properly, while the soft- ware-programmable brownout detector allows detection of either a battery discharge ...
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Figure 10-2. Clock Generator Block Diagram 10.6 Power Management Controller The Power Management Controller provides all the clock signals to the system. It provides: • the Processor Clock, HCLK • the Free running processor clock, FCLK • the Cortex SysTick ...
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Figure 10-3. Power Management Controller Block Diagram The SysTick calibration value is fixed at 8000, which allows the generation of a time base with SysTick clock at 8 MHz (max HCLK MHz/8) 10.7 Watchdog Timer ...
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Real-Time Timer • Real-Time Timer, allowing backup of time with different accuracies – 32-bit Free-running backup Counter – Integrates a 16-bit programmable prescaler running on slow clock – Alarm Register capable to generate a wake-up of the system through ...
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... Chip Identification • Chip Identifier (CHIPID) registers permit recognition of the device and its revision. Table 10-1. SAM3S8B (Rev A) SAM3S8C (Rev A) SAM3SD8B (Rev A) SAM3SD8C (Rev A) • JTAG ID: 0x05B2D03F 10.14 UART • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – ...
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Lock of the configuration by the connected peripheral • Synchronous output, provides set and clear of several I/O lines in a single write • Write Protect Registers • Programmable Schmitt trigger inputs • Parallel capture mode – Can be ...
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Table 10-3. Peripheral Identifiers (Continued) Instance ID Instance Name 22 SSC 23 TC0 24 TC1 25 TC2 26 TC3 27 TC4 28 TC5 29 ADC 30 DACC 31 PWM 32 CRCCU 33 ACC 34 UDP 10.17 Peripheral Signal Multiplexing on ...
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PIO Controller A Multiplexing Table 10-4. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A Peripheral B PA0 PWMH0 TIOA0 PA1 PWMH1 TIOB0 PA2 PWMH2 SCK0 PA3 TWD0 NPCS3 PA4 TWCK0 TCLK0 PA5 RXD0 NPCS3 PA6 TXD0 PCK0 ...
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PIO Controller B Multiplexing Table 10-5. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A Peripheral B PB0 PWMH0 PB1 PWMH1 PB2 URXD1 NPCS2 PB3 UTXD1 PCK2 PB4 TWD1 PWMH2 PB5 TWCK1 PWML0 PB6 PB7 PB8 PB9 PB10 ...
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PIO Controller C Multiplexing Table 10-6. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A PC0 D0 PC1 D1 PC2 D2 PC3 D3 PC4 D4 PC5 D5 PC6 D6 PC7 D7 PC8 NWE PC9 NANDOE PC10 NANDWE PC11 ...
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Embedded Peripherals Overview 11.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash – Serial peripherals, such ...
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USART • Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial communications – stop bits in Asynchronous Mode stop bits in Synchronous Mode – Parity generation and ...
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Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two ...
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One programmable Fault Input providing an asynchronous protection of outputs • Stepper motor control (2 Channels) 11.8 High Speed Multimedia Card Interface (HSMCI) • 4-bit or 1-bit Interface • Compatibility with MultiMedia Card Specification Version 4.3 • Compatibility with ...
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Single ended/differential conversion • Programmable gain 11.11 Digital-to-Analog Converter (DAC) • channel 12-bit DAC • mega-samples conversion rate in single channel mode • Flexible conversion range • Multiple trigger sources ...
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Temperature Sensor – ADVREF – AD0 to AD3 ADC channels • Plus input selection: – All analog inputs • output selection: – Internal signal – external pin – selectable inverter • window function • Interrupt on: – Rising edge, ...
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Package Drawings The SAM3S8/SD8 series devices are available in LQFP, QFN and TFBGA packages. Figure 12-1. 100-lead LQFP Package Mechanical Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information. ...
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Figure 12-2. 100-ball TFBGA Package Mechanical Drawing 11090AS–ATARM–10-Feb-12 SAM3S8/SD8 Summary 51 ...
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Figure 12-3. 64-lead LQFP Package Mechanical Drawing SAM3S8/SD8 Summary 52 11090AS–ATARM–10-Feb-12 ...
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Figure 12-4. 64-lead QFN Package Mechanical Drawing 11090AS–ATARM–10-Feb-12 SAM3S8/SD8 Summary 53 ...
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... Ordering Information Table 13-1. Ordering Codes for SAM3S8/SD8 Devices Ordering Code MRL ATSAM3S8CA-AU A ATSAM3S8CA-CU A ATSAM3S8BA-AU A ATSAM3S8BA-MU A ATSAM3SD8CA-AU A ATSAM3SD8CA-CU A ATSAM3SD8BA-AU A ATSAM3SD8BA-MU A SAM3S8/SD8 Summary 54 Flash (Kbytes) Package (Kbytes) 512 QFP100 512 BGA100 512 QFP64 512 QFN64 512 QFP100 512 BGA100 512 QFP64 512 QFN64 ...
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Revision History In the table that follows, the most recent version of the document is referenced first. Doc. Rev Comments First issue 11090AS–ATARM–10-Feb-12 SAM3S8/SD8 Summary Change Request Ref. 55 ...
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