SAM3SD8B Atmel Corporation, SAM3SD8B Datasheet - Page 25

• Manufacturer Part Number: SAM3SD8B
• Manufacturer: Atmel Corporation

7.5
7.6
11090AS–ATARM–10-Feb-12
Master to Slave Access
Peripheral DMA Controller
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths
are forbidden or simply not wired, and shown as “-” in the following table.
Table 7-3.
The Peripheral DMA Controller handles transfer requests from the channel according to the fol-
lowing priorities (Low to High priorities):
Table 7-4.
• Handles data transfer between peripherals and memories
• Low bus arbitration overhead
• Next Pointer management for reducing interrupt latency requirement
Instance name
Slaves
USART2
USART2
USART1
USART0
0
1
2
3
4
UART1
UART0
– One Master Clock cycle needed for a transfer from memory to peripheral
– Two Master Clock cycles needed for a transfer from peripheral to memory
DACC
PWM
TWI1
TWI0
SPI
SAM3S8_SD8 Master to Slave Access
Peripheral DMA Controller
External Bus Interface
Peripheral Bridge
Internal SRAM
Internal Flash
Internal ROM
Channel T/R
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Transmit
Receive
Masters
Cortex-M3 I/D
SAM3S8/SD8 Summary
Bus
0
X
X
-
-
-
Cortex-M3 S
Bus
X
X
X
1
-
-
PDC
2
X
X
X
X
-
CRCCU
X
X
X
X
3
-
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