SAM3X8C Atmel Corporation, SAM3X8C Datasheet - Page 1099

• Manufacturer Part Number: SAM3X8C
• Manufacturer: Atmel Corporation

39.5.3.11
Figure 39-26. Example of an OUT Pipe with one Data Bank
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
UOTGHS_HSTPIPIMRx.FIFOCON
UOTGHS_HSTPIPISRx.TXOUTI
Management of OUT Pipes
OUT packets are sent by the host. All data which acknowledges or not the bank can be written
when it is full.
The pipe must be configured and unfrozen first.
The Transmitted OUT Data Interrupt (UOTGHS_HSTPIPISRx.TXOUTI) bit is set at the same
time as UOTGHS_HSTPIPIMRx.FIFOCON when the current bank is free. This triggers a PEP_x
interrupt if the Transmitted OUT Data Interrupt Enable (UOTGHS_HSTPIPIMRx.TXOUTE) bit is
one.
UOTGHS_HSTPIPISRx.TXOUTI shall be cleared by software (by writing a one to the Transmit-
ted OUT Data Interrupt Clear (UOTGHS_HSTPIPIDRx.TXOUTIC) bit) to acknowledge the
interrupt, which has no effect on the pipe FIFO.
The user then writes into the FIFO and clears the UOTGHS_HSTPIPIDRx.FIFOCON bit to allow
the UOTGHS to send the data. If the OUT pipe is composed of multiple banks, this also switches
to the next bank. The UOTGHS_HSTPIPISRx.TXOUTI and UOTGHS_HSTPIPIMRx.FIFOCON
bits are updated in accordance with the status of the next bank.
U O T G H S _ H S T P I P I S R x . T X O U T I s h a l l a l w a y s b e c l e a r e d b e f o r e c l e a r i n g
UOTGHS_HSTPIPIMRx.FIFOCON.
The UOTGHS_HSTPIPISRx.RWALL bit is set when the current bank is not full, i.e., the software
can write further data into the FIFO.
Notes:
SW
1. If the user decides to switch to the Suspend state (by writing a zero to the
2. In High-Speed operating mode, the host controller automatically manages the PING protocol
write data to CPU
UOTGHS_HSTCTRL.SOFE bit) while a bank is ready to be sent, the UOTGHS automatically
exits this state and the bank is sent.
to maximize the USB bandwidth. The user can tune the PING protocol by handling the Ping
Enable (PINGEN) bit and the bInterval Parameter for the Bulk-Out/Ping Transaction (BINTER-
VALL) field in UOTGHS_HSTPIPCFGx. See the
BANK 0
SW
OUT
(bank 0)
DATA
Section 39.6.3.13
HW
ACK
SW
write data to CPU
for more details.
BANK 0
SAM3X/A
SAM3X/A
SW
OUT
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