SAM3X8C Atmel Corporation, SAM3X8C Datasheet - Page 1177
SAM3X8C
Manufacturer Part Number
SAM3X8C
Description
Manufacturer
Atmel Corporation
- Current page: 1177 of 1465
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39.6.3.12
Name:
Address:
Access:
• PRSTx: Pipe x Reset
Writing a one to this bit will reset the Pipe x FIFO.
This resets the endpoint x registers (UOTGHS_HSTPIPCFGx, UOTGHS_HSTPIPISRx, UOTGHS_HSTPIPIMRx) but not
the endpoint configuration (ALLOC, PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ).
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle management.
The endpoint configuration remains active and the endpoint is still enabled.
Writing a zero to this bit will complete the reset operation and allow to start using the FIFO.
• PENx: Pipe x Enable
Writing a one to this bit will enable the Pipe x.
Writing a zero to this bit will disable the Pipe x, which forces the Pipe x state to inactive and resets the pipe x registers
(UOTGHS_HSTPIPCFGx, UOTGHS_HSTPIPISRx, UOTGHS_HSTPIPIMRx) but not the pipe configuration
(UOTGHS_HSTPIPCFGx.ALLOC, UOTGHS_HSTPIPCFGx.PBK, UOTGHS_HSTPIPCFGx.PSIZE).
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
PRST7
PEN7
31
23
15
–
–
7
Host Pipe Register
UOTGHS_HSTPIP
0x400AC41C
Read-write
PRST6
PEN6
30
22
14
–
–
6
PRST5
PEN5
29
21
13
–
–
5
PRST4
PEN4
28
20
12
–
–
4
PRST3
PEN3
27
19
11
–
–
3
PRST2
PEN2
26
18
10
–
–
2
PRST1
PEN1
25
17
–
9
–
1
SAM3X/A
SAM3X/A
PRST8
PRST0
PEN8
PEN0
24
16
8
0
1177
1177
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