SAM3X8C Atmel Corporation, SAM3X8C Datasheet - Page 1218

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SAM3X8C

Manufacturer Part Number
SAM3X8C
Description
Manufacturer
Atmel Corporation
Datasheets
40.7.4.3
1218
1218
Error Interrupt Handler
SAM3X/A
SAM3X/A
Overload
Refer to the Bosch CAN specification v2.0 for details on fault confinement.
WARN, BOFF, ERRA and ERRP (CAN_SR) represent the current status of the CAN bus and
are not latched. They reflect the current TEC and REC (CAN_ECR) values as described in
tion “Fault Confinement” on page
Based on that, if these bits are used as an interrupt, the user can enter into an interrupt and not
see the corresponding status register if the TEC and REC counter have changed their state.
When entering Bus Off Mode, the only way to exit from this state is 128 occurrences of 11 con-
secutive recessive bits or a CAN controller reset.
In Error Active Mode, the user reads:
In Error Passive Mode, the user reads:
In Bus Off Mode, the user reads:
The CAN interrupt handler should do the following:
The overload frame is provided to request a delay of the next data or remote frame by the
receiver node (“Request overload frame”) or to signal certain error conditions (“Reactive over-
load frame”) related to the intermission field respectively.
Reactive overload frames are transmitted after detection of the following error conditions:
The CAN controller can generate a request overload frame automatically after each message
sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in the
CAN_MR register.
Reactive overload frames are automatically handled by the CAN controller even if the OVL bit in
the CAN_MR register is not set. An overload flag is generated in the same way as an error flag,
but error counters do not increment.
• ERRA =1
• ERRP = 0
• BOFF = 0
• ERRA = 0
• ERRP =1
• BOFF = 0
• ERRA = 0
• ERRP =1
• BOFF =1
• Only enable one error mode interrupt at a time.
• Look at and check the REC and TEC values in the interrupt handler to determine the current
• Detection of a dominant bit during the first two bits of the intermission field
• Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit
state.
by a receiver or a transmitter at the last bit of an error or overload frame delimiter
1217.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Sec-

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