AD9739 Analog Devices, AD9739 Datasheet - Page 19

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
The
(MSB) first and least significant bit (LSB) first data formats.
Figure 35 illustrates how the serial port words are formed for
the MSB first and LSB first modes. The bit order is controlled
by the SDIO_DIR bit (Register 0x00, Bit 7). The default value is 0,
MSB first. When the LSB first bit is set high, the serial port
interprets both instruction and data bytes LSB first.
SDATA
SDATA
SCLK
SCLK
CS
CS
AD9739
Figure 35. SPI Timing, MSB First (Upper) and LSB First (Lower)
R/W
A0
N1
A1 A2
serial port can support both most significant bit
INSTRUCTION CYCLE
INSTRUCTION CYCLE
N2
A4
A3
A3 A2
A4
N2
A1
N1
SCLK
SCLK
SCLK
R/W
SDIO
SDO
SDIO
SDIO
A0
CS
CS
CS
D7
D0
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
1
1
D6
D1
1
1
t
t
t
DS
DS
DS
t
t
t
t
t
t
HI
S
S
HI
S
HI
Figure 37. SPI 3-Wire Read Operation Timing
Figure 38. SPI 4-Wire Read Operation Timing
1/
1/
1/
D1
D6
R/W
R/W
R/W
t
t
t
Figure 36. SPI Write Operation Timing
f
f
f
DH
DH
DH
SCLK
SCLK
N
N
SCLK
D7
D0
N
N
N1
N1
t
t
t
LOW
N1
LOW
LOW
Rev. B | Page 19 of 48
A2
A2
N0
A1
A1
A0
A0
A0
Figure 36 illustrates the timing requirements for a write operation
to the SPI port. After the serial port enable ( CS ) signal goes low,
data (SDIO) pertaining to the instruction header is read on the
rising edges of the clock (SCLK). To initiate a write operation,
the read/not-write bit is set low. After the instruction header is
read, the eight data bits pertaining to the specified register are
shifted into the SDIO pin on the rising edge of the next eight
clock cycles.
Figure 37 illustrates the timing for a 3-wire read operation to
the SPI port. After CS goes low, data (SDIO) pertaining to the
instruction header is read on the rising edges of SCLK. A read
operation occurs if the read/not-write indicator is set high. After
the address bits of the instruction header are read, the eight data
bits pertaining to the specified register are shifted out of the SDIO
pin on the falling edges of the next eight clock cycles.
Figure 38 illustrates the timing for a 4-wire read operation to
the SPI port. The timing is similar to the 3-wire read operation
with the exception that data appears at the SDO pin only, while the
SDIO pin remains at high impedance throughout the operation.
The SDO pin is an active output only during the data transfer
phase and remains three-stated at all other times.
t
t
DV
DV
D7
D7
D7
D6
D6
D6
D1
D1
D1
D0
D0
t
H
D0
t
t
t
EZ
EZ
EZ
AD9739