AD9739 Analog Devices, AD9739 Datasheet - Page 28

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9739
LVDS DATA PORT INTERFACE
The
using dual LVDS data ports. The interface is source synchronous
and double data rate (DDR) where the host provides an embedded
data clock input (DCI) at f
aligned with the data transitions. The data format is offset binary;
however, twos complement format can be realized by reversing
the polarity of the MSB differential trace. As shown in Figure 40,
the host feeds the
two 14-bit LVDS data ports (DB0 and DB1) at ½ the DAC clock
rate (that is, f
then generates a phase shifted version of DCI to register the
input data on both the rising and falling edges.
PROCESSOR
As shown in Figure 41, the DCI clocks edges must be coincident
with the data bit transitions with minimum skew, jitter, and
intersymbol interference. To ensure coincident transitions with the
data bits, the DCI signal should be implemented as an additional
data line with an alternating (010101…) bit sequence from the
same output drivers used for the data. Maximizing the opening
of the eye in both the DCI and data signals improves the reliability
of the data port interface. Differential controlled impedance traces
of equal length (that is, delay) should also be used between the
host processor and
HOST
Figure 40. Recommended Digital Interface Between the
AD9739
DAC
supports input data rates from 1.6 GSPS to 2.5 GSPS
/2). The
AD9739
f
f
DATA
f
EVEN DATA
DCO
AD9739
ODD DATA
DCI
SAMPLES
SAMPLES
14 × 2
14 × 2
1 × 2
1 × 2
=
=
=
AD9739
f
f
f
DAC
DAC
DAC
Host Processor
DAC
with deinterleaved input data into
/4
AND DB1[13:0]
/4
/2
input to limit bit-to-bit skew.
/4 with its rising and falling edges
DB0[13:0]
internal data receiver controller
DCI
DCO
DCI
AD9739
DIV-BY-4
Figure 41. LVDS Data Port Timing Requirements
AD9739
t
VALID
and
f
2 × 1
DAC
t
Rev. B | Page 28 of 48
VALID
+
/f
t
GUARD
DAC
The maximum allowable skew and jitter out of the host
processor with respect to the DCI clock edge on each LVDS
port is calculated as
MaxSkew + Jitter = Period(ns) − ValidWindow(ps) − Guard
where ValidWindow(ps) is represented by t
represented by t
The minimum specified LVDS valid window is 344 ps, and a
guard band of 100 ps is recommended. Therefore, at the maximum
operating frequency of 2.5 GSPS, the maximum allowable FPGA
and PCB bit skew plus jitter is equal to 356 ps.
For synchronous operation, the
output, DCO, to the host at the same rate as DCI (that is, f
to maintain the lowest skew variation between these clock
domains. Since the DCO signal is generated from a separate
clock divider, its phase relationship relative to the f
used by the data receiver controller will vary upon each power-up.
Applications sensitive to this phase ambiguity (resulting in a ±2
DACCLK pipeline variation) should consider using the sync
controller.
The host processor has a worst-case skew between DCO and
DCI that is both implementation and process dependent. This
worst-case skew can also vary an additional 30% over temperature
and supply corners. The delay line within the data receiver
controller can track a ±1.5 ns skew variation after initial lock.
While it is possible for the host to have an internal PLL that
generates a synchronous f
derived, digital implementations that result in the shortest
propagation delays result in the lowest skew variation.
The data receiver controller is used to ensure proper data hand-off
between the host and
The circuit shown in Figure 42 functions as a delay lock loop in
which a 90
to sample the input data into the DDR receiver registers. This
ensures that the sampling instance occurs in the middle of the
data pattern eyes (assuming matched DCI and DBx[13:0] delays).
Note that, because the DCI delay and sample delay clocks are
derived from the div-by-4 circuitry, this 90° phase relationship
holds as long as the delay settings (that is, DCI_DEL, SMP_DEL)
are also matched.
o
phase shifted version of the DCI clock input is used
GUARD
= 800 ps − 344 ps − 100 ps
= 356 ps
MAX SKEW
+ JITTER
in Figure 41.
AD9739
DAC
/4 from which the DCI signal is
internal digital clock domains.
AD9739
provides a data clock
VALID
Data Sheet
and Guard is
DAC
/4 clocks
DAC
/4)