AD9739 Analog Devices, AD9739 Datasheet - Page 5

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
LVDS DIGITAL SPECIFICATIONS
VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I
1996 reduced range link, unless otherwise noted.
Table 2.
Parameter
LVDS DATA INPUTS (DB0[13:0], DB1[13:0])
LVDS CLOCK INPUT (DCI and SYNC_IN)
LVDS CLOCK OUTPUT (DCO and SYNC_OUT)
1
2
3
DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins.
DCI_P and DCI_N pins, as well as SYNC_IN_P and SYNC_IN_N pins.
DCO_P and DCO_N pins, as well as SYNC_OUT_P/SYNC_OUT_N pins with 100 Ω differential termination.
Input Common-Mode Voltage Range, V
Logic High Differential Input Threshold, V
Logic Low Differential Input Threshold, V
Receiver Differential Input Impedance, R
Input Capacitance
LVDS Input Rate
LVDS Minimum Data Valid Period, t
Input Common-Mode Voltage Range, V
Logic High Differential Input Threshold, V
Logic Low Differential Input Threshold, V
Receiver Differential Input Impedance, R
Input Capacitance
Maximum Clock Rate
Output Voltage High (x_P or x_N)
Output Voltage Low (x_P or x_N)
Output Differential Voltage, |V
Output Offset Voltage, V
Output Impedance, Single-Ended, R
R
Maximum Clock Rate
O
Single-Ended Mismatch
OS
OD
|
VALID
O
2
1
(See Figure 41)
COM
COM
IN
IN
IL_DTH
IL_DTH
IH_DTH
IH_DTH
3
OUTFS
= 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.3-
Rev. B | Page 5 of 48
Min
825
175
−175
80
1250
825
175
−175
80
625
1025
150
1150
80
625
Typ
400
−400
1.2
400
−400
1.2
200
100
Max
1575
120
344
1575
120
1375
250
1250
120
10
AD9739
Unit
mV
mV
mV
Ω
pF
MSPS
ps
mV
mV
mV
Ω
pF
MHz
mV
mV
mV
mV
Ω
%
MHz