AD9739 Analog Devices, AD9739 Datasheet - Page 20

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9739
SPI REGISTER MAP
Table 9. Full Register Map (N/A = Not Applicable)
Name
Mode
Power-
Down
CNT_
CLK_DIS
IRQ_EN
IRQ_REQ
RSVD
FSC_1
FSC_2
DEC_
CNT
RSVD
LVDS_
CNT
DIG_
STAT
LVDS_
STAT1
LVDS_
STAT2
RSVD
RSVD
LVDS_
REC_
CNT1
LVDS_
REC_
CNT2
LVDS_
REC_
CNT3
LVDS_
REC_
CNT4
LVDS_
REC_
CNT5
LVDS_
REC_
CNT6
LVDS_
REC_
CNT7
LVDS_
REC_
CNT8
LVDS_
REC_
CNT9
LVDS_
REC_
STAT1
LVDS_
REC_
STAT2
Hex
Addr
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
Bit 7
SDIO_DIR
N/A
N/A
N/A
N/A
N/A
FSC[7]
Sleep
N/A
N/A
N/A
HNDOFF_
Fall[3]
SUP/HLD_
Edge1
SUP/HLD_
SYNC
N/A
N/A
SYNC_
FLG_RST
SMP_DEL[1]
SMP_DEL[9]
DCI_DEL[3]
CLKDIVPH[1]
SYNC_
GAIN[1]
N/A
SYNCSH_
DEL[0]
SYNCSH_
DEL[8]
SMP_DEL[1]
SMP_DEL[9]
Bit 6
LSB/MSB
N/A
N/A
N/A
N/A
N/A
FSC[6]
N/A
N/A
N/A
N/A
HNDOFF_
Fall[2]
N/A
SUP/HLD_
Edge0
N/A
N/A
SYNC_
LOOP_ON
SMP_
DEL[0]
SMP_
DEL[8]
DCI_
DEL[2]
CLKDIVPH[0]
SYNC_
GAIN[0]
SYNCO_
DEL[6]
N/A
SYNCSH_
DEL[7]
SMP_DEL[0]
SMP_
DEL[8]
Bit 5
Reset
LVDS_
DRVR_PD
N/A
SYNC_
LST_EN
SYNC_
LST_IRQ
N/A
FSC[5]
N/A
N/A
N/A
N/A
HNDOFF_
Fall[1]
DCI_
PHS3
SYNC_
SAMP1
N/A
N/A
SYNC_
MST/SLV
FINE_
DEL_
MID[3]
SMP_
DEL[7]
DCI_
DEL[1]
DCI_
DEL[9]
SYNCOUT_
PH[1]
SYNCO_
DEL[5]
N/A
SYNCSH_
DEL[6]
N/A
SMP_
DEL[7]
Rev. B | Page 20 of 48
Bit 4
N/A
LVDS_
RCVR_PD
N/A
SYNC_
LCK_EN
SYNC_
LCK_IRQ
N/A
FSC[4]
N/A
N/A
N/A
N/A
HNDOFF_
Fall[0]
DCI_
PHS1
SYNC_
SAMP0
N/A
N/A
SYNC_
CNT_ENA
FINE_
DEL_
MID[2]
SMP_
DEL[6]
DCI_
DEL[0]
DCI_
DEL[8]
SYNCOUT_
PH[0]
SYNCO_
DEL[4]
N/A
SYNCSH_
DEL[5]
N/A
SMP_
DEL[6]
Bit 3
N/A
N/A
CLKGEN_PD
MU_LST_EN
MU_LST_
IRQ
N/A
FSC[3]
N/A
N/A
N/A
HNDOFF_
CHK_RST
HNDOFF_
Rise[3]
DCI_PRE_
PH2
LVDS1_HI
N/A
N/A
N/A
FINE_DEL_
MID[1]
SMP_
DEL[5]
FINE_DEL_
SKW[3]
DCI_
DEL[7]
LCKTHR[3]
SYNCO_
DEL[3]
N/A
SYNCSH_
DEL[4]
SMP_
FINE_
DEL[3]
SMP_
DEL[5]
Bit 2
N/A
N/A
N/A
MU_LCK_EN
MU_LCK_
IRQ
N/A
FSC[2]
N/A
N/A
N/A
N/A
HNDOFF_
Rise[2]
DCI_PRE_
PH0
LVDS1_LO
N/A
N/A
RCVR_
FLG_RST
FINE_DEL_
MID[0]
SMP_
DEL[4]
FINE_DEL_
SKW[2]
DCI_
DEL[6]
LCKTHR[2]
SYNCO_
DEL[2]
N/A
SYNCSH_
DEL[3]
SMP_
FINE_
DEL[2]
SMP_
DEL[4]
CLK_
REC_CNT_
RCV_
FSC[1]
FSC[9]
DAC_DEC[1]
LVDS0_HI
Bit 1
N/A
RCVR_PD
CLK
LST_EN
RCVLST_
IRQ
N/A
N/A
LVDS_
Bias[1]
HNDOFF_
Rise[1]
DCI_PST_
PH2
N/A
N/A
RCVR_
LOOP_ON
RCVR_
GAIN[1]
SMP_
DEL[3]
FINE_DEL_
SKW[1]
DCI_
DEL[5]
LCKTHR[1]
SYNCO_
DEL[1]
N/A
SYNCSH_
DEL[2]
SMP_
FINE_
DEL[1]
SMP_
DEL[3]
Bit 0
N/A
DAC_
BIAS_PD
MU_CNT_
CLK
RCV_
LCK_EN
RCVLCK_
IRQ
N/A
FSC[0]
FSC[8]
DAC_DEC[0]
N/A
LVDS_
Bias[0]
HNDOFF_
Rise[0]
DCI_PST_
PH0
LVDS0_LO
N/A
N/A
RCVR_
CNT_ENA
RCVR_
GAIN[0]
SMP_
DEL[2]
FINE_DEL_
SKW[0]
DCI_
DEL[4]
LCKTHR[0]
SYNCO_
DEL[0]
N/A
SYNCSH_
DEL[1]
SMP_
FINE_
DEL[0]
SMP_
DEL[2]
Data Sheet
0x00
0x00
0x03
0x00
0x00
N/A
0x00
0x02
0x00
N/A
0x00
RNDM
RNDM
RNDM/0
N/A
N/A
0x42
0xDD
0x29
0x71
0x0A
0x42
0x00
0x00
0x00
0xC7
0x29
Default