AD9739 Analog Devices, AD9739 Datasheet - Page 23

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Data Sheet
TxDAC FULL-SCALE CURRENT SETTING (I
Table 14. TxDAC Full-Scale Current Setting (I
Address
(Hex)
0x06
0x07
TxDAC QUAD-SWITCH MODE OF OPERATION
Table 15. TxDAC Quad-Switch Mode of Operation Register
Address
(Hex)
0x08
DCI PHASE ALIGNMENT STATUS
Table 16. DCI Phase Alignment Status Register
Address
(Hex)
0x0C
SYNC_IN PHASE ALIGNMENT STATUS
Table 17. SYNC_IN Phase Alignment Status Register
Address
(Hex)
0x0D
DATA RECEIVER CONTROLLER CONFIGURATION
Table 18. Data Receiver Controller Configuration Register
Address
(Hex)
0x10
Name
SYNC_FLG_RST
SYNC_LOOP_ON
SYNC_MST/SLV
SYNC_CNT_ENA
RCVR_FLG_RST
RCVR_LOOP_ON
RCVR_CNT_ENA
Name
DCI_PRE_PH0
DCI_PST_PH0
Name
FSC_1
FSC_2
Sleep
Name
SYNC_IN_PH90
SYNC_IN_PH0
Name
DAC-DEC
Bit
[7:0]
[1:0]
7
Bit
2
0
7
6
5
4
2
0
Bit
1
R/W
R/W
R/W
R/W
R/W
R
R
R/W
W
R/W
R/W
R/W
W
R/W
R/W
Bit
5
4
Bit
[1:0]
Default
Setting
0x00
0x02
Default
Setting
0
0
0
0
0
0
0
Default
Setting
1
1
R
R
R/W
OUTFS
OUTFS
R/W
R/W
) and Sleep Register
Comments
Sets the TxDAC I
I
0 = enable DAC output, 1 = disable DAC output (sleep).
Default
Setting
0
0
OUTFS
Comments
0 = DCI rising edge is after the PRE delayed version of the Phase 0 sampling edge.
1 = DCI rising edge is before the PRE delayed version of the Phase 0 sampling edge.
0 = DCI rising edge is after the POST delayed version of the Phase 0 sampling edge.
1 = DCI rising edge is before the POST delayed version of the Phase 0 sampling edge.
Comments
Sync controller flag reset. Write 1 followed by 0 to reset flags.
0 = disable, 1 = enable. Enable for master only. When enabled, sync controller
generates an IRQ when master falls out of lock and automatically begins
search/track routine.
Sync controller configuration. 0 = slave, 1 = master.
Sync controller enable. 0 = disable, 1 = enable
Data receiver controller flag reset. Write 1 followed by 0 to reset flags.
0 = disable, 1 = enable. When enabled, the data receiver controller generates an IRQ;
it falls out of lock and automatically begins a search/track routine.
Data receiver controller enabled. 0 = disable, 1 = enable.
) AND SLEEP
= 0.0226 × FSC[9:0] + 8.58, where FSC = 0 to 1023.
Rev. B | Page 23 of 48
Default
Setting
0x00
Comments
0 = SYNCIN rising edge is after Phase 90 sampling edge.
1 = SYNCIN rising edge is before Phase 90 sampling edge.
0 = SYNCIN rising edge is after Phase 0 sampling edge.
1 = SYNCIN rising edge is before Phase 0 sampling edge.
OUTFS
current between 8 mA and 31 mA (default = 20 mA).
Comments
0x00 = normal baseband mode.
0x01 = return-to-zero mode.
0x02 = mix mode.
AD9739