AD9739 Analog Devices, AD9739 Datasheet - Page 38

• Manufacturer Part Number: AD9739
• Description: 14-Bit, 2500 MSPS, RF Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9739

• Resolution (bits): 14bit
• Dac Update Rate: 2.5GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9739
ANALOG INTERFACE CONSIDERATIONS
ANALOG MODES OF OPERATION
The
The quad-switch architecture masks the code-dependent glitches
that occur in a conventional two-switch DAC. Figure 55 compares
the waveforms for a conventional DAC and the quad-switch
DAC. In the two-switch architecture, a code-dependent glitch
occurs each time the DAC switches to a different state (that is,
D1 to D2). This code-dependent glitching causes an increased
amount of distortion in the DAC. In a quad-switch architecture
(no matter what the codes are), there are always two switches
transitioning at each half clock cycle, thus eliminating the code-
dependent glitches. However, a constant glitch occurs at 2 ×
DACCLK because half of the internal switches change state on
the rising DACCLK edge, while the other half change state on
the falling DACCLK edge.
Another attribute of the quad-switch architecture is that it also
enables the DAC core to operate in one of the following three
modes: normal mode, mix mode, and return-to-zero (RZ) mode.
The mode is selected via SPI Register 0x08, Bits[1:0] with
normal mode being the default value. In the mix mode, the
output is effectively chopped at the DAC sample rate. This has
the effect of reducing the power of the fundamental signal while
increasing the power of the images centered around the DAC
sample rate, thus improving the output power of these images.
The RZ mode is similar to the analog mix mode, except that the
intermediate data samples are replaced with midscale values.
(NORMAL MODE)
DACCLK_x
DBx[13:0]
FOUR-SWITCH
AD9739
TWO-SWITCH
DAC OUTPUT
DAC OUTPUT
DACCLK_x
Figure 55. Two-Switch and Quad-Switch DAC Waveforms
INPUT
DATA
uses the quad-switch architecture shown in Figure 54.
Figure 54.
LATCHES
CLK
D
D
D
1
1
1
D
D
D
2
V
V
V
V
AD9739
2
2
G
G
G
G
1
2
3
4
D
D
D
3
3
3
D
V
Quad-Switch Architecture
D
D
4
G
4
4
1
IOUTP
D
D
D
5
5
5
D
D
D
6
6
6
V
D
G
D
D
7
V
2
7
7
DD
V
D
D
D
G
8
3
8
8
D
D
D
9
IOUTN
9
9
D
D
D
10
10
10
V
G
t
t
4
Rev. B | Page 38 of 48
Figure 56 shows the DAC waveforms for both the mix mode
and the RZ mode. Note that the disadvantage of the RZ mode
is the 6 dB loss of power to the load because the DAC is only
functioning for ½ the DAC update period. This ability to change
modes provides the user the flexibility to place a carrier anywhere
in the first three Nyquist zones, depending on the operating
mode selected. Switching between the analog modes reshapes
the sinc roll-off inherent at the DAC output. The maximum
amplitude in all three Nyquist zones is impacted by this sinc
roll-off, depending on where the carrier is placed (see Figure 57).
As a practical matter, the usable bandwidth in the third Nyquist
zone becomes limited at higher DAC clock rates (that is, >2 GSPS)
when the output bandwidth of DAC core and the interface
network (that is, balun) contributes to additional roll-off.
FOUR-SWITCH
FOUR-SWITCH
(
DAC OUTPUT
f
DAC OUTPUT
ZERO MODE)
S
(RETURN TO
MIX MODE)
DACCLK_x
–10
–15
–20
–25
–30
–35
–5
0
0FS
INPUT
Figure 57. Sinc Roll-Off for Each Analog Operating Mode
DATA
RZ MODE
NYQUIST ZONE
Figure 56. Mix-Mode and RZ DAC Waveforms
D
FIRST
0.25FS
D
1
D
1
–D
1
D
1
D
2
D
2
–D
2
D
0.50FS
2
D
3
D
3
–D
3
D
FREQUENCY (Hz)
3
NYQUIST ZONE
D
4
D
4
–D
MIX MODE
4
SECOND
D
4
0.75FS
D
5
D
5
–D
5
5
D
D
6
D
6
–D
6
NORMAL
6
D
1.00FS
D
MODE
7
D
7
–D
7
D
7
D
NYQUIST ZONE
8
8
D
–D
8
D
8
1.25FS
D
Data Sheet
THIRD
9
9
D
–D
9
D
9
D
10
10
D
–D
10
10
1.50FS
t
t