ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 40

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

ADuC7124/ADuC7126
on P0.5 (see the General-Purpose Input/Output section) if
enabled in the ADCCON register.
ADCDAT Register
Name:
Address:
Default Value:
Access:
ADCDAT is an ADC data result register that holds the 12-bit
ADC result, as shown in Figure 30.
ADCRST Register
Name:
Address:
Default Value:
Access:
ADCRST resets the digital interface of the ADC. Writing any value
to this register resets all the ADC registers to their default values.
ADCGN Register
Name:
Address:
Default Value:
Access:
ADCGN is a 10-bit gain calibration register.
ADCOF Register
Name:
Address:
Default Value:
Access:
ADCOF is a 10-bit offset calibration register.
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture can operate in three different modes: differential,
pseudo differential, and single-ended.
Differential Mode
The ADuC7124/ADuC7126 each contains a successive approx-
imation ADC based on two capacitive DACs. Figure 32 and
Figure 33 show simplified schematics of the ADC in acquisition
and conversion phases, respectively. The ADC comprises con-
trol logic, a SAR, and two capacitive DACs. In Figure 32 (the
acquisition phase), SW3 is closed and SW1 and SW2 are in
ADCDAT
0xFFFF0510
0x00000000
Read only
ADCRST
0xFFFF0514
0x00
Read/write
ADCGN
0xFFFF0530
0x0200
Read/write
ADCOF
0xFFFF0534
0x0200
Read/write
Rev. B | Page 40 of 104
Position A. The comparator is held in a balanced condition, and
the sampling capacitor arrays acquire the differential signal on
the input.
When the ADC starts a conversion, as shown in Figure 33, SW3
opens, and then SW1 and SW2 move to Position B. This causes
the comparator to become unbalanced. Both inputs are discon-
nected once the conversion begins. The control logic and the
charge redistribution DACs are used to add and subtract fixed
amounts of charge from the sampling capacitor arrays to bring
the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC output code. The output
impedances of the sources driving the V
be matched; otherwise, the two inputs have different settling
times, resulting in errors.
AIN11
Pseudo Differential Mode
In pseudo differential mode, Channel− is linked to the
ADCNEG pin of the ADuC7124/ADuC7126. In Figure 34,
ADCNEG is represented as V
(Channel−) and B (V
to ground or to a low voltage. The input signal on V
vary from V
that V
AIN11
AIN11
AIN0
AIN0
AIN0
V
IN–
REF
MUX
MUX
MUX
+ V
CHANNEL+
CHANNEL–
CHANNEL+
CHANNEL–
IN−
CHANNEL+
CHANNEL–
IN−
Figure 34. ADC in Pseudo Differential Mode
to V
do not exceed AV
Figure 32. ADC Acquisition Phase
Figure 33. ADC Conversion Phase
REF
REF
B
A
A
B
B
A
A
B
B
A
A
B
V
V
V
+ V
REF
REF
REF
SW1
SW2
SW1
SW2
SW1
SW2
). The ADCNEG pin must be connected
IN−
C
C
C
C
C
C
. Note that V
S
S
S
S
S
S
IN−
. SW2 switches between A
DD
.
SW3
SW3
SW3
COMPARATOR
COMPARATOR
COMPARATOR
IN+
IN−
and V
must be chosen so
IN–
CAPACITIVE
CAPACITIVE
CAPACITIVE
CAPACITIVE
CAPACITIVE
CAPACITIVE
IN+
pins must
CONTROL
CONTROL
CONTROL
DAC
LOGIC
DAC
DAC
LOGIC
DAC
DAC
LOGIC
DAC
can then