ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 97

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

XMCFG Register
Name:
Address:
Default Value:
Access:
XMCFG is set to 1 to enable external memory access. This must
be set to 1 before any port pins can function as external memory
access pins. The port pins must also be individually enabled via
the GPxCON MMR.
Table 147. XMxCON Registers
Name
XM0CON
XM1CON
XM2CON
XM3CON
XMxCON are the control registers for each memory region.
They allow the enabling/disabling of a memory region and
control the data bus width of the memory region.
Table 148. XMxCON MMR Bit Descriptions
Bit
1
0
Table 149. XMxPAR Registers
Name
XM0PAR
XM1PAR
XM2PAR
XM3PAR
Description
Selects data bus width.
Set by the user to select a 16-bit data bus.
Cleared by the user to select an 8-bit data bus.
Enables memory region.
Set by the user to enable memory region.
Cleared by the user to disable the memory region.
Address
0xFFFFF010
0xFFFFF014
0xFFFFF018
0xFFFFF01C
Address
0xFFFFF020
0xFFFFF024
0xFFFFF028
0xFFFFF02C
XMCFG
0xFFFFF000
0x00
Read/write
Default Value
0x00
0x00
0x00
0x00
Default Value
0x70FF
0x70FF
0x70FF
0x70FF
Access
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
Rev. B | Page 97 of 104
XMxPAR are registers that define the protocol used for
accessing the external memory for each memory region.
Table 150. XMxPAR MMR Bit Descriptions
Bit
15
[14:12]
11
10
9
8
[7:4]
[3:0]
Figure 58, Figure 59, Figure 60, and Figure 61 show the timing
for a read cycle, a read cycle with address hold and bus turn
cycles, a write cycle with address and write hold cycles, and a
write cycle with wait sates, respectively.
Description
Enable byte write strobe. This bit is only used for two
8-bit memory blocks sharing the same memory region.
Set by the user to gate the A0 output with the WS
output. This allows byte write capability without using
BHE and BLE
Cleared by user to use
Number of wait states on the address latch enable strobe.
Reserved.
Extra address hold time.
Set by the user to disable extra hold time.
Cleared by the user to enable one clock cycle of hold
on the address in read and write.
Extra bus transition time on read.
Set by the user to disable extra bus transition time.
Cleared by the user to enable one extra clock before
and after the read strobe (RS).
Extra bus transition time on write.
Set by the user to disable extra bus transition time.
Cleared by the user to enable one extra clock before and
after the write strobe (WS).
Number of write wait states.
Select the number of wait states added to the length of
the WS pulse. 0x0 is 1 clock; 0xF is 16 clock cycles (default
value).
Number of read wait states.
Select the number of wait states added to the length of
the RS pulse. 0x0 is 1 clock; 0xF is 16 clock cycles
(default value).
signals.
ADuC7124/ADuC7126
BHE and BLE signals.