ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 71

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

Master Mode
In master mode, the I2CxADR0 register is programmed with
the I
In 7-bit address mode, I2CxADR0[7:1] are set to the device
address. I2CxADR0[0] is the read/write bit.
In 10-bit address mode, the 10-bit address is created as follows:
I2CxADR0[7:3] must be set to 11110b.
I2CxADR0[2:1] = Address Bits[9:8].
I2CxADR1[7:0] = Address Bits[7:0].
I2CxADR0[0] is the read/write bit.
I
The I
These are described in the I2C Master Registers section.
Table 102. I2CxMCON MMR Bit Descriptions
Bit
[15:9]
8
7
6
5
4
3
2
1
0
2
C Registers
2
C address of the device.
2
C peripheral interfaces consists of a number of MMRs.
Name
I2CMCENI
I2CNACKENI
I2CALENI
I2CMTENI
I2CMRENI
I2CMSEN
I2CILEN
I2CBD
I2CMEN
Description
Reserved. These bits are reserved and should not be written to.
I
Set this bit to enable an interrupt on detecting a stop condition on the I
Clear this bit to clear the interrupt source.
I
Set this bit to enable interrupts when the I
Clear this bit to clear the interrupt source.
I
Set this bit to enable interrupts when the I
Clear this bit to clear the interrupt source.
I
Set this bit to enable interrupts when the I
Clear this bit to clear the interrupt source.
I
Set this bit to enable interrupts when the I
Cleared by user to disable interrupts when the I
I
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
Clear this bit to disable clock stretching.
I
Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their
respective input signals.
Cleared by the user to disable loopback mode.
I
Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start
condition.
Clear this bit to wait until the I
I
Set by the user to enable I
Clear this bit to disable I
2
2
2
2
2
2
2
2
2
C transmission complete interrupt enable bit.
C no acknowledge (NACK) received interrupt enable bit.
C arbitration lost interrupt enable bit.
C transmit interrupt enable bit.
C receive interrupt enable bit.
C master SCL stretch enable bit.
C internal loopback enable.
C master backoff disable bit.
C master enable bit.
2
C master mode.
2
C master mode.
2
C bus becomes free.
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2
2
2
2
C master receives a NACK.
C master is unable to gain control of the I
C master has transmitted a byte.
C master receives data.
2
C master is receiving data.
I
I
Name:
Address:
Default
Value:
Access:
Function:
2
2
C Master Registers
C Master Control Register
I2C0MCON, I2C1MCON
0xFFFF0800, 0xFFFF0900
0x0000, 0x0000
Read/write
This 16-bit MMR configures the I
master mode.
2
C bus.
ADuC7124/ADuC7126
2
C bus.
2
C peripheral in