CS8422-CNZ Cirrus Logic Inc, CS8422-CNZ Datasheet - Page 41

• Manufacturer Part Number: CS8422-CNZ
• Description: IC SAMPLE RATE CONVERTER 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8422-CNZ

• Package / Case: 32-QFN
• Applications: Digital Audio
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: SMD/SMT
• Package: 32QFN
• Operating Temperature: -55 to 125 °C
• Audio Control Type: Sample Rate Converter
• Control Interface: I2C, SPI
• Supply Voltage Range: 1.71V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Audio Ic Case Style: QFN
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1568 - BOARD EVAL FOR CS8422 RCVR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1732

DS692F1
determines what the output sample rate will be based on the MCLK selected for SDOUT1, as shown in the
hardware control pin descriptions shown above. For SDOUT2, the output sample rate is dictated by the in-
coming AES3 data, and the master mode clock ratio determines the frequency of RMCK relative to the in-
coming AES3 sample rate. Note: if TDM Mode is selected for SDOUT1, then SDOUT1 cannot be set to
“Master, Fso = MCLK/128”.
32.4 k ± 1% to GND
16.2 k ± 1% to GND
8.06 k ± 1% to GND
4.02 k ± 1% to GND
1.96 k ± 1% to GND
1.0 k + 1% to GND
32.4 k ± 1% to VL
16.2 k ± 1% to VL
8.06 k ± 1% to VL
4.02 k ± 1% to VL
1.96 k ± 1% to VL
1.0 k + 1% to VL
SAOF pin
127.0 k ± 1% to GND
63.4 k ± 1% to GND
32.4 k ± 1% to GND
16.2 k ± 1% to GND
8.06 k ± 1% to GND
4.02 k ± 1% to GND
1.96 k ± 1% to GND
1.0 k + 1% to GND
127.0 k ± 1% to VL
63.4 k ± 1% to VL
32.4 k ± 1% to VL
16.2 k ± 1% to VL
8.06 k ± 1% to VL
4.02 k ± 1% to VL
1.96 k ± 1% to VL
1.0 k + 1% to VL
MS_SEL pin
Table 5. Hardware Mode Serial Audio Port Clock Control
Table 4. Hardware Mode Serial Audio Format Control
Right-Justified 24-bit data
Right-Justified 20-bit data
Right-Justified 16-bit data
Left-Justified 24-bit data
Left-Justified 20-bit data
Left-Justified 16-bit data
SDOUT1 Data Format
TDM Mode 24-bit data
TDM Mode 20-bit data
TDM Mode 16-bit data
(Master mode only)
(Master mode only)
(Master mode only)
I²S 24-bit data
I²S 20-bit data
I²S 16-bit data
Master, Fso = MCLK/128
Master, Fso = MCLK/256
Master, Fso = MCLK/512
Master, Fso = MCLK/128
Master, Fso = MCLK/256
Master, Fso = MCLK/512
Master, Fso = MCLK/128
Master, Fso = MCLK/256
Master, Fso = MCLK/512
Master, Fso = MCLK/128
Master, Fso = MCLK/256
Master, Fso = MCLK/512
SDOUT1
Slave
Slave
Slave
Slave
RMCK = 256 x Fsi
RMCK = 128 x Fsi
RMCK = 256 x Fsi
RMCK = 512 x Fsi
Master Mode,
Master Mode,
Master Mode,
SDOUT2 Data Format
SDOUT2
(Master mode only)
(Master mode only)
(Master mode only)
Slave
Right-Justified
Right-Justified
Right-Justified
Left-Justified
Left-Justified
Left-Justified
I²S
I²S
I²S
I²S
I²S
I²S
CS8422
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