CS8422-CNZ Cirrus Logic Inc, CS8422-CNZ Datasheet - Page 55

• Manufacturer Part Number: CS8422-CNZ
• Description: IC SAMPLE RATE CONVERTER 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8422-CNZ

• Package / Case: 32-QFN
• Applications: Digital Audio
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: SMD/SMT
• Package: 32QFN
• Operating Temperature: -55 to 125 °C
• Audio Control Type: Sample Rate Converter
• Control Interface: I2C, SPI
• Supply Voltage Range: 1.71V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Audio Ic Case Style: QFN
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1568 - BOARD EVAL FOR CS8422 RCVR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1732

DS692F1
11.13 Serial Audio Output Data Format - SDOUT2 (0Dh)
SOMS2
7
0
SORES1[1:0] - Resolution of the output data on SDOUT
SOFSEL1[1:0] - Format of the output data on SDOUT
TDM[1:0] - Enable the time-division multiplexing (TDM) through TDM_IN and either SDOUT1 or SDOUT2.
See
SOMS2 - Master/Slave Mode Selector
SOSF2 - OSCLK2 Frequency. Valid only in master mode (SOMS2 = 1). If the SRC is selected as the source
for SDOUT2 (SDOUT2[1:0] = 00 in register 0Ah), then the master clock (MCLK) is the SAO MCLK (as se-
lected by the SAO_MCLK bit in register 08h). If the AES3 receiver is selected as the source for SDOUT2
(SDOUT2[1:0] = 01 in register 0Ah), then the MCLK is RMCK. Should be changed when PDN = 1. See
Table 10
then SAI_CLK[3:0] determine the MCLK/OLRCK1 ratio.
00 - 24-bit resolution.
01 - 20-bit resolution.
10 - 18-bit resolution.
11 - 16-bit resolution
00 - Left-Justified
01 - I²S
10 - Right-Justified (Master mode only)
11 - AES3 Direct. Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits.
The time slot occupied by the Z bit is used to indicate the location of the block start. Only valid if serial port
sourced directly by the AES3-compatible receiver.
00 - TDM Mode not enabled. Serial audio format selected by SOFSEL1[1:0]
01 - TDM Mode enabled through TDM_IN and SDOUT1. SOFSEL1[1:0] has no effect in this mode.
10 - TDM Mode enabled through TDM_IN and SDOUT2. SOFSEL2[1:0] has no effect in this mode.
11 - Reserved
0 - Serial audio output port is in slave mode. OSCLK and OLRCK are inputs.
1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs.
“Time Division Multiplexing (TDM) Mode” on page 27
for details. Note: If serial output 2 is in master mode and sourced directly by the serial input port,
SOSF2
SAI_CLK[3:0], or
SAO_CLK[3:0],
6
0
RMCK[3:0]
0000
0001
Table 10. OSCLK2/OLRCK2 Ratios and SOSF2 Settings
SORES2_1
5
0
MCLK/OLRCK2 Ratio
SORES2_0
4
0
64
96
SOFSEL2_1
3
0
for more details.
SOSF2 = 0
OSCLK2/OLRCK2 Ratio
SOFSEL2_0
64
48
2
0
SOSF2 = 1
INVALID
Reserved
96
1
Reserved
CS8422
0
55