CS8422-CNZ Cirrus Logic Inc, CS8422-CNZ Datasheet - Page 18

• Manufacturer Part Number: CS8422-CNZ
• Description: IC SAMPLE RATE CONVERTER 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8422-CNZ

• Package / Case: 32-QFN
• Applications: Digital Audio
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: SMD/SMT
• Package: 32QFN
• Operating Temperature: -55 to 125 °C
• Audio Control Type: Sample Rate Converter
• Control Interface: I2C, SPI
• Supply Voltage Range: 1.71V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Audio Ic Case Style: QFN
• No. Of Pins: 32
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1568 - BOARD EVAL FOR CS8422 RCVR
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1732

18
Notes:
TDM Mode OSCLK Falling Edge to OLRCK Edge
RMCK/MCLK_OUT Output Frequency (VL = 1.8 V)
RMCK/MCLK_OUT Output Frequency (VL = 2.5 V)
RMCK/MCLK_OUT Output Duty Cycle (VL = 1.8 V)
RMCK/MCLK_OUT Output Duty Cycle (VL = 2.5 V)
Slave Mode
ISCLK Frequency
ISCLK High Time
ISCLK Low Time
OSCLK Frequency
OSCLK High Time
OSCLK Low Time
I/OLRCK Edge to I/OSCLK Rising Edge
I/OSCLK Rising Edge to I/OLRCK Edge
OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid
SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge
SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge
TDM Mode OLRCK High Time
TDM Mode OLRCK Rising Edge to OSCLK Rising Edge
TDM Mode OSCLK Rising Edge to OLRCK Falling Edge
Master Mode
I/OSCLK Frequency (non-TDM Mode)
I/OLRCK Duty Cycle
I/OSCLK Duty Cycle
I/OSCLK Falling Edge to I/OLRCK Edge
OSCLK Falling Edge to SDOUT Output Valid (VL = 1.8 V)
OSCLK Falling Edge to SDOUT Output Valid (VL = 2.5 V)
SDIN Setup Time Before I/OSCLK Rising Edge
SDIN Hold Time After I/OSCLK Rising Edge
TDM Mode OSCLK Frequency
TDM Mode OSCLK Falling Edge to OLRCK Edge (VL = 1.8V)
TDM Mode OSCLK Falling Edge to OLRCK Edge (VL = 2.5V)
7. After powering up the CS8422, RST should be held low until the power supplies and clocks are settled.
8. If ISCLK is selected as the clock source for the PLL, then the Sample Rate = ISCLK/64.
(Note 11)
Parameter
(Note 10)
(Note 12)
VL = 1.8 V, 2.5 V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
sckh
sckh
lrckh
t
t
lckd
t
t
fsm
sckl
sckl
lcks
dpd
t
lcks
dpd
dpd
t
fsm
fsm
fsh
fss
ds
dh
ds
dh
48*Fsi/o
28.7
28.7
Min
9.2
9.2
7.4
6.2
4.7
7.3
7.0
6.2
4.7
7.3
37
45
20
45
45
-
-
-
-
-
-
-
-
-
-
-
-
Typ
50
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
128*Fsi/o
49.152
Max
13.5
15.7
29.5
11.2
4.2
5.7
6.4
9.6
5.7
31
63
55
55
55
31
-
-
-
-
-
-
-
-
-
-
-
-
-
CS8422
DS692F1
Units
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
%