ST72324J6 STMicroelectronics, ST72324J6 Datasheet - Page 107

• Manufacturer Part Number: ST72324J6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324J6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

10-BIT A/D CONVERTER (ADC) (Cont’d)
10.6.3 Functional Description
The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.
If the input voltage (V
(high-level voltage reference) then the conversion
result is FFh in the ADCDRH register and 03h in
the ADCDRL register (without overflow indication).
If the input voltage (V
level voltage reference) then the conversion result
in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of
the conversion is stored in the ADCDRH and AD-
CDRL registers. The accuracy of the conversion is
described in the Electrical Characteristics Section.
R
for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.
10.6.3.1 A/D Converter Configuration
The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.
In the ADCCSR register:
10.6.3.2 Starting the Conversion
In the ADCCSR register:
– Set the ADON bit to enable the A/D converter
When a conversion is complete:
A read to the ADCDRH resets the EOC bit.
AIN
and to start the conversion. From this time on,
the ADC performs a continuous conversion of
the selected channel.
– Select the CS[3:0] bits to assign the analog
– The EOC bit is set by hardware.
– The result is in the ADCDR registers.
channel to convert.
is the maximum recommended impedance
AIN
AIN
) is lower than V
) is greater than V
SSA
(low-
AREF
To read the 10 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRL register
3. Read the ADCDRH register. This clears EOC
Note: The data is not latched, so both the low and
the high data register must be read before the next
conversion is complete, so it is recommended to
disable interrupts while reading the conversion re-
sult.
To read only 8 bits, perform the following steps:
1. Poll the EOC bit
2. Read the ADCDRH register. This clears EOC
10.6.3.3 Changing the conversion channel
The application can change channels during con-
version. When software modifies the CH[3:0] bits
in the ADCCSR register, the current conversion is
stopped, the EOC bit is cleared, and the A/D con-
verter starts converting the newly selected chan-
nel.
10.6.4 Low Power Modes
Note: The A/D converter may be disabled by re-
setting the ADON bit. This feature allows reduced
power consumption when no conversion is need-
ed.
10.6.5 Interrupts
None.
Mode
WAIT
HALT
automatically.
automatically.
Description
No effect on A/D Converter
A/D Converter disabled.
After wakeup from Halt mode, the A/D
Converter requires a stabilization time
t
before accurate conversions can be
performed.
STAB
(see Electrical Characteristics)
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