ST72324J6 STMicroelectronics, ST72324J6 Datasheet - Page 14

• Manufacturer Part Number: ST72324J6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324J6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72324Jx ST72324Kx
Table 2. Hardware Register Map
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1
Address
000Ch
000Dh
002Ch
002Dh
000Ah
000Bh
000Eh
000Fh
002Ah
002Bh
002Eh
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
0010h
0011h
0012h
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
0030h
to
to
WATCHDOG
Port D
Port A
Port B
Port E
Port F
FLASH
Port C
Block
MCC
SPI
ITC
SI
2)
2)
2)
2)
2)
PADR
PADDR
PAOR
PBDR
PBDDR
PBOR
PCDR
PCDDR
PCOR
PDADR
PDDDR
PDOR
PEDR
PEDDR
PEOR
PFDR
PFDDR
PFOR
SPIDR
SPICR
SPICSR
ISPR0
ISPR1
ISPR2
ISPR3
EICR
FCSR
WDGCR
SICSR
MCCSR
MCCBCR
Register
Label
Port A Data Register
Port A Data Direction Register
Port A Option Register
Port B Data Register
Port B Data Direction Register
Port B Option Register
Port C Data Register
Port C Data Direction Register
Port C Option Register
Port D Data Register
Port D Data Direction Register
Port D Option Register
Port E Data Register
Port E Data Direction Register
Port E Option Register
Port F Data Register
Port F Data Direction Register
Port F Option Register
SPI Data I/O Register
SPI Control Register
SPI Control/Status Register
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
External Interrupt Control Register
Flash Control/Status Register
Watchdog Control Register
System Integrity Control Status Register
Main Clock Control / Status Register
Main Clock Controller: Beep Control Register
Reserved Area (15 Bytes)
Reserved Area (3 Bytes)
Register Name
Status
Reset
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
7Fh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0xh
00h
00h
00h
00h
00h
xxh
xxh
1)
1)
1)
1)
1)
1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Remarks
2)
2)