ST72324J6 STMicroelectronics, ST72324J6 Datasheet - Page 160

• Manufacturer Part Number: ST72324J6
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324J6

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator, clock security system and bypass for external clock
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• 16-bit Timer A With: 1 input capture, 1 output compare, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72324Jx ST72324Kx
KNOWN LIMITATIONS (Cont’d)
To avoid this, a semaphore is set to '1' before
checking the level change. The semaphore is
changed to level '0' inside the interrupt routine.
When a level change is detected, the semaphore
status is checked and if it is '1' this means that the
last interrupt has been missed. In this case, the in-
terrupt routine is invoked with the call instruction.
There is another possible case, that is, if writing to
PxOR or PxDDR is done with global interrupts dis-
abled (interrupt mask bit set). In this case, the
semaphore is changed to '1' when the level
change is detected. Detecting a missed interrupt is
done after the global interrupts are enabled (inter-
rupt mask bit reset) and by checking the status of
the semaphore. If it is '1' this means that the last
interrupt was missed and the interrupt routine is in-
voked with the call instruction.
To implement the workaround, the following soft-
ware sequence is to be followed for writing into the
PxOR/PxDDR registers. The example is for Port
PF1 with falling edge interrupt sensitivity. The soft-
ware sequence is given for both cases (global in-
terrupt disabled/enabled).
Case 1: Writing to PxOR or PxDDR with Global In-
terrupts Enabled:
LD A,#01
LD sema,A
LD A,PFDR
AND A,#02
LD X,A
PxOR/PxDDR
LD A,#$90
LD PFDDR,A ; Write to PFDDR
LD A,#$ff
LD PFOR,A
LD A,PFDR
AND A,#02
LD Y,A
PxOR/PxDDR
LD A,X
cp A,#02
jrne OUT
TNZ Y
jrne OUT
LD A,sema
edge is detected
CP A,#01
160/164
1
; set the semaphore to '1'
; store the level before writing to
; store the level after writing to
; check for falling edge
; check the semaphore status if
; Write to PFOR
jrne OUT
call call_routine; call the interrupt routine
OUT:LD A,#00
LD sema,A
.call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt
LD A,#00
LD sema,A
IRET
Case 2: Writing to PxOR or PxDDR with Global In-
terrupts Disabled:
SIM
LD A,PFDR
AND A,#$02
LD X,A
PxOR/PxDDR
LD A,#$90
LD PFDDR,A ; Write into PFDDR
LD A,#$ff
LD PFOR,A
LD A,PFDR
AND A,#$02
LD Y,A
PxOR/PxDDR
LD A,X
cp A,#$02
jrne OUT
TNZ Y
jrne OUT
LD A,#$01
LD sema,A
detected
RIM
LD A,sema
CP A,#$01
jrne OUT
call call_routine; call the interrupt routine
RIM
OUT:
; entry to call_routine
; entry to interrupt routine
; set the interrupt mask
; store the level before writing to
; store the level after writing to
; check for falling edge
; set the semaphore to '1' if edge is
; check the semaphore status
RIM
; reset the interrupt mask
; Write to PFOR