ST7MC2M9 STMicroelectronics, ST7MC2M9 Datasheet - Page 104

• Manufacturer Part Number: ST7MC2M9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

Specifications of ST7MC2M9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST7MC1xx/ST7MC2xx
10.4.8 Register Description
SPI CONTROL REGISTER (SPICR)
Read/Write
Reset Value: 0000 xxxx (0xh)
Bit 7 = SPIE
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End
Bit 6 = SPE
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see
(MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the ex-
ternal pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2
This bit is set and cleared by software and is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to
Mode SCK
0: Divider by 2 enabled
1: Divider by 2 disabled
Note: This bit has no effect in slave mode.
Bit 4 = MSTR
This bit is set and cleared by software. It is also
cleared by hardware when, in master mode,
SS = 0 (see
(MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin
104/309
1
SPIE
of Transfer event, Master Mode Fault or Over-
run error occurs (SPIF = 1, MODF = 1 or
OVR = 1 in the SPICSR register)
changes from an input to an output and the func-
tions of the MISO and MOSI pins are reversed.
7
SPE
Frequency.
Section 10.4.5.1 Master Mode Fault
Section 10.4.5.1 Master Mode Fault
SPR2 MSTR CPOL CPHA SPR1
Table 18 SPI Master
SPR0
0
Bit 3 = CPOL
This bit is set and cleared by software. This bit de-
termines the idle state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note: If CPOL is changed at the communication
byte boundaries, the SPI must be disabled by re-
setting the SPE bit.
Bit 2 = CPHA
This bit is set and cleared by software.
0: The first clock transition is the first data capture
1: The second clock transition is the first capture
Note: The slave must have the same CPOL and
CPHA settings as the master.
Bits 1:0 = SPR[1:0]
These bits are set and cleared by software. Used
with the SPR2 bit, they select the baud rate of the
SPI serial clock SCK output by the SPI in master
mode.
Note: These 2 bits have no effect in slave mode.
Table 18. SPI Master Mode SCK Frequency
edge.
edge.
Serial Clock
f
f
f
f
CPU
f
f
CPU
CPU
CPU
CPU
CPU
/128
/16
/32
/64
/4
/8
SPR2
1
0
1
0
SPR1
0
1
SPR0
0
1
0
1