ST7MC2M9 STMicroelectronics, ST7MC2M9 Datasheet - Page 42

• Manufacturer Part Number: ST7MC2M9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

Specifications of ST7MC2M9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST7MC1xx/ST7MC2xx
INTERRUPTS (Cont’d)
7.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the Wait
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the Halt modes (see column “Exit from
Halt” in “Interrupt Mapping” table). When several
pending interrupts are present while exiting Halt
mode, the first one serviced can only be an inter-
rupt with exit from Halt mode capability and it is se-
lected through the same decision process shown
in
Note: If an interrupt, that is not able to Exit from
Halt mode, is pending with the highest priority
when exiting Halt mode, this interrupt is serviced
after the first one serviced.
Figure 22. Concurrent Interrupt Management
Figure 23. Nested Interrupt Management
42/309
1
Figure
21.
11 / 10
11 / 10
MAIN
MAIN
RIM
RIM
IT2
IT2
IT1
IT1
IT4
MCES
MCES
IT1
IT4
IT0
IT0
7.4 CONCURRENT & NESTED MANAGEMENT
The following
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, MCES. The software priority
is given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
IT3
IT3
IT1
23. The interrupt hardware priority is given
IT4
IT2
Figure 22
10
10
SOFTWARE
PRIORITY
LEVEL
SOFTWARE
PRIORITY
LEVEL
MAIN
MAIN
and
3
3
3
3
3
3
3/0
3
3
2
1
3
3
3/0
Figure 23
I1
I1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 0
0 1
1 1
1 1
show two
I0
I0