ST7MC2M9 STMicroelectronics, ST7MC2M9 Datasheet - Page 33

• Manufacturer Part Number: ST7MC2M9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

Specifications of ST7MC2M9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.3.2 Auxiliary Voltage Detector (AVD)
The Voltage Detector function (AVD) is based on
an analog comparison between a V
V
ply. The V
lower than the V
age in order to avoid parasitic detection (hystere-
sis).
The output of the AVD comparator is directly read-
able by the application software through a real-
time status bit (AVDF) in the SICSR register. This
bit is read only.
Caution: The AVD function is active only if the
LVD is enabled through the option byte (see
tion 14.1 on page
6.3.2.1 Monitoring the V
If the AVD interrupt is enabled, an interrupt is gen-
erated when the voltage crosses the V
V
Figure 18. Using the AVD to Monitor V
IT+(AVD)
IT-(AVD)
AVDF bit
AVD INTERRUPT
REQUEST
IF AVDIE bit = 1
LVD RESET
V
V
V
V
IT+(AVD)
IT+(LVD)
IT-(LVD)
IT-(AVD)
threshold (AVDF bit toggles).
reference value and the V
IT-
reference value for falling voltage is
V
DD
IT+
290).
reference value for rising volt-
0
DD
Main Supply
DD
INTERRUPT PROCESS
IT-(AVD)
IT+(AVD)
main sup-
V
Early Warning Interrupt
(Power has dropped, MCU not
not yet in reset)
DD
hyst
sec-
and
or
1
In the case of a drop in voltage, the AVD interrupt
acts as an early warning, allowing software to shut
down safely before the LVD resets the microcon-
troller. See
The interrupt on the rising edge is used to inform
the application that the V
If the voltage rise time t
CPU cycles (depending on the reset delay select-
ed by option byte), no AVD interrupt will be gener-
ated when V
If t
– If the AVD interrupt is enabled before the
– If the AVD interrupt is enabled after the V
V
rupts will be received: the first when the AVDIE
bit is set, and the second when the threshold is
reached.
threshold is reached then only one AVD interrupt
will occur.
rv
IT+(AVD)
is greater than 256 or 4096 cycles then:
threshold is reached, then 2 AVD inter-
Figure
IT+(AVD)
t
18.
rv
VOLTAGE RISE TIME
is reached.
ST7MC1xx/ST7MC2xx
rv
DD
is less than 256 or 4096
warning state is over.
INTERRUPT PROCESS
0
IT+(AVD)
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