ST7MC2M9 STMicroelectronics, ST7MC2M9 Datasheet - Page 190

• Manufacturer Part Number: ST7MC2M9
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

Specifications of ST7MC2M9

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.9 Channel Manager
The channel manager consists of:
– A Phase State register with preload and polarity
Figure 108. Channel Manager Block Diagram
190/309
1
OCV bit
CLIM bit
CLI bit
Sampling frequency
function
PWM Generator
Current comparator
* = Preload register, changes taken into account at next C event.
1
1
MPHST Register
output
CFF[2:0] bits
MPAR Register
MCFR Register
MCRA Register
1
MREF Register
HFRQ[2:0] bits
HFE[1:0] bits
OE[5:0] bits
DAC bit
OO bits*
MPOL Register
MCRA Register
OP[5:0] bits
MOE bit
C
V
I
6
5
Filter
6
6
6
1
PWM generator
Dead
Time
MCRA Register
V0C1 bit
S Q
R
High frequency chopper
Sampling
Clock
Phase
OFF time
Channel [5:0]
Channel [5:0]
– A multiplexer to direct the PWM to the low and/
– A tristate buffer asynchronously driven by an
The block diagram is shown in
or high channel group
emergency input
Sensorless Sensor
Dead
Time
n
Register*
“1”
V
I
x6
x6
Dead
Time
D
R
Notes:
Reg
Reg
C
E
O
Z
S,H
V
1
2
+/-
I
n
8
Voltage Mode
events:
Commutation
BEMF Zero-crossing
End Of Demagnetization
Emergency Stop
Ratio Updated (+1 or -1)
Multiplier Overflow
Branch taken after C event
Branch taken after D event
Current Mode
3
2
Figure
Updated/Shifted on R
Updated with Reg
MDTG Register
MCRA Register
MCRB Register
OS[2:0] bits*
SR bit
108.
n+1
on C