ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 103

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

ST72324Bxx
Figure 55. Clearing the WCOL bit (Write collision flag) software sequence
Single master systems
A typical single master system may be configured, using an MCU as the master and four
MCUs as slaves (see
The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to be
inputs at that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line the master allows only one active slave
device during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master will receive the previous byte back from the slave device if all MISO and
MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
Figure 56. Single master/multiple slave configuration
2nd Step
Clearing sequence after SPIF = 1 (end of a data byte transfer)
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
5V
SCK
SCK
MOS
SS
MOSI
Read SPICSR
Read SPIDR
Maste
MCU
I
Slave
MCU
Figure
MISO
MISO
r
1st Step
2nd Step
SS
56).
WCOL = 0
SPIF = 0
Result
Read SPICSR
Read SPIDR
SCK
MOSI
MCU
Slave
MISO
SS
WCOL = 0
Result
SCK
MOSI
Slave
MCU
MISO
SS
Note: Writing to the SPIDR register
instead of reading it does not reset
the WCOL bit.
On-chip peripherals
SCK
MOSI
Slave
MCU
MISO
SS
103/193