ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 90

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

On-chip peripherals
90/193
Table 49.
Control Register 2 (CR2)
Table 50.
CR2
Bit
Bit
M
4
3
2
1
0
7
6
OC1E
R/W
7
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
Name
Name
OC2E
OCIE
CR1 register description (continued)
CR2 register description
Forced Output compare 2
Forced Output compare 1
Output Level 2
Input Edge 1
Output Level 1
OC2E
Output compare 1 pin enable
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in
Output Compare mode, both OLV1 and OLV2 in PWM and One-Pulse mode).
Whatever the value of the OC1E bit, the Output Compare 1 function of the timer
remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Output compare 2 pin enable
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in
Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2
function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
R/W
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and
even if there is no successful comparison.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if
there is no successful comparison.
This bit is copied to the OCMP2 pin whenever a successful comparison occurs with
the OC2R register and OCxE is set in the CR2 register. This value is copied to the
OCMP1 pin in One Pulse mode and Pulse Width modulation mode.
This bit determines which type of level transition on the ICAP1 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison
occurs with the OC1R register and the OC1E bit is set in the CR2 register.
6
OPM
R/W
5
PWM
R/W
4
Function
Function
3
CC[1:0]
R/W
2
Reset value: 0000 0000 (00h)
IEDG2
R/W
1
ST72324Bxx
EXEDG
R/W
0