ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 29

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

ST72324Bxx
Table 6.
Table 7.
Table 8.
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (ISPRx). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.
See
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
BIt Name
BIt Name
1
0
5
3
Section 7: Interrupts on page 41
I1
I0
C
Z
Zero (Arithmetic Management bit)
Carry/borrow
Software Interrupt Priority 1
Software Interrupt Priority 0
Arithmetic management bits (continued)
Software interrupt bits
Interrupt software priority selection
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the ‘bit test and branch’, shift and rotate instructions.
The combination of the I1 and I0 bits determines the current interrupt software priority
(see
The combination of the I1 and I0 bits determines the current interrupt software priority
(see
Interrupt software priority
Table
Table
8).
8).
for more details.
Function
Function
Central processing unit (CPU)
Level
High
Low
I1
1
0
0
1
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I0
0
1
0
1