ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 37

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

ST72324Bxx
Note:
6.5.2
Caution:
1
2
3
4
Provided the minimum V
MCU can only be in two modes:
In these conditions, secure operation is always ensured for the application without the need
for external reset hardware.
During an LVD reset, the RESET pin is held low, thus permitting the MCU to reset other
devices.
The LVD allows the device to be used without any external reset circuitry.
If the medium or low thresholds are selected, the detection may occur outside the specified
operating voltage range. Below 3.8 V, device operation is not guaranteed.
The LVD is an optional function which can be selected by option byte.
It is recommended to make sure that the V
device is exiting from reset, to ensure the application functions properly.
Figure 16. Low voltage detector vs reset
AVD (auxiliary voltage detector)
The AVD is based on an analog comparison between a V
value and the V
V
The output of the AVD comparator is directly readable by the application software through a
real-time status bit (AVDF) in the SICSR register. This bit is read only.
The AVD function is active only if the LVD is enabled through the option byte (see
Section 14.1 on page
Monitoring the V
The AVD voltage threshold value is relative to the selected LVD threshold configured by
option byte (see
If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the
V
In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing
software to shut down safely before the LVD resets the microcontroller. See
IT+
IT+(AVD)
reference value for rising voltage in order to avoid parasitic detection (hysteresis).
–
–
RESET
under full software control
in static safe reset
or V
V
V
IT-
IT+
IT-(AVD)
V
DD
DD
Section 14.1 on page
main supply. The V
DD
threshold (AVDF bit toggles).
179).
main supply
DD
value (guaranteed for the oscillator frequency) is above V
IT-
179).
reference value for falling voltage is lower than the
DD
supply voltage rises monotonously when the
V
hys
Supply, reset and clock management
IT-(AVD)
and V
IT+(AVD)
Figure
reference
17.
IT-
37/193
, the