ST72324BJ6 STMicroelectronics, ST72324BJ6 Datasheet - Page 69

• Manufacturer Part Number: ST72324BJ6
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BJ6

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

ST72324Bxx
10.1.9
10.2
10.2.1
Control register (WDGCR)
Table 35.
Table 36.
Main clock controller with real-time clock and beeper
(MCC/RTC)
The main clock controller consists of three different functions:
●
●
●
Each function can be used independently and simultaneously.
Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal
peripherals. It manages Slow power saving mode (see
for more details).
The prescaler selects the f
MCCSR register: CP[1:0] and SMS.
WDGCR
Address (Hex.) Register label
Bit
6:0
7
WDGA
R/W
a programmable CPU clock prescaler
a clock-out signal to supply external devices
a real-time clock timer with interrupt capability
7
002Ah
WDGA
Name
T[6:0]
WDGCR register description
Watchdog timer register map and reset values
Activation bit
7-bit counter (MSB to LSB)
This bit is set by software and only cleared by hardware after a reset. When
WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watchdog option is enabled by option byte.
These bits contain the value of the Watchdog counter, which is decremented every
16384 f
(T6 is cleared).
6
WDGCR
reset value
OSC2
CPU
cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh
5
main clock frequency and is controlled by three bits in the
WDGA
7
0
4
T6
6
1
Function
T[6:0]
T5
R/W
5
1
3
Section 8.2: Slow mode on page 52
T4
4
1
2
Reset value: 0111 1111 (7Fh)
T3
3
1
On-chip peripherals
T2
2
1
1
T1
1
1
0
69/193
T0
0
1