ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 101

• Manufacturer Part Number: ST72324BK2
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BK2

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

ST72324Bxx
10.4.4
Note:
Note:
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an Overrun condition (see
(OVR) on page
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (see
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge
Figure 54
The diagram may be interpreted as a master or slave timing diagram where the SCK, MISO
and MOSI pins are directly connected between the master and the slave device.
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Figure 54. Data clock timing diagram
1. This figure should not be used as a replacement for parametric information. Refer to the Electrical
Characteristics chapter.
Figure
(from master)
(from slave)
MISO
(from slave)
SCK
(CPOL = 0)
MOSI
Capture strobe
(CPOL = 1)
SCK
(CPOL = 0)
(from master)
Capture strobe
(CPOL = 1)
(to slave)
SCK
MISO
MOSI
SCK
SS
(to slave)
SS
shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
102).
54).
MSB
MSB
MSB
MSB
Bit 6
Bit 6
Bit 6
Bit 6
Bit 5
Bit 5
Bit 5
Bit 5
(1)
CPHA = 0
CPHA = 1
Bit 4
Bit 4
Bit 4
Bit 4
Bit3
Bit3
Bit3
Bit3
Bit 2
Bit 2
Bit 2
Bit 2
Bit 1
Bit 1
Bit 1
Bit 1
On-chip peripherals
LSB
LSB
LSB
Overrun condition
LSB
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