ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 78
ST72324BK2
Manufacturer Part Number
ST72324BK2
Description
5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72324BJ6.pdf
(193 pages)
Specifications of ST72324BK2
Hdflash Endurance
1 kcycle at 55 °C, data retention 40 years at 85 °C
Clock Sources
crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
4 Power Saving Modes
Slow, Wait, Active-halt, and Halt
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On-chip peripherals
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External clock
The external clock (where available) is selected if CC0 = 1 and CC1 = 1 in the CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 38. Counter timing diagram, internal clock divided by 2
Figure 39. Counter timing diagram, internal clock divided by 4
Figure 40. Counter timing diagram, internal clock divided by 8
The MCU is in reset state when the internal reset signal is high, when it is low the MCU is
running.
Timer Overflow Flag (TOF)
Timer Overflow Flag (TOF)
Timer Overflow Flag (TOF)
Counter register
Internal reset
Counter register
Counter register
Timer clock
CPU clock
Internal reset
Internal reset
Timer clock
Timer clock
CPU clock
CPU clock
FFFC
FFFC
FFFD FFFE FFFF 0000 0001 0002 0003
FFFD
FFFD
0000
0001
0000
ST72324Bxx
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