ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 22

• Manufacturer Part Number: ST72324BK2
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BK2

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

Register and memory map
Table 3.
1. The bits associated with unavailable pins must always keep their reset value.
2. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
22/193
Address
0058h to
004Ah
004Bh
004Ch
004Dh
004Eh
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
006Fh
0070h
0071h
0072h
0073h
007Fh
I/O pins are returned instead of the DR register contents.
Timer B
Hardware register map (continued)
Legend: x = undefined, R/W = read/write
Block
ADC
SCI
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
ADCCSR
ADCDRH
ADCDRL
Register label
Timer B control register 2
Timer B control register 1
Timer B control/status register
Timer B input capture 1 high register
Timer B input capture 1 low register
Timer B output compare 1 high register
Timer B output compare 1 low register
Timer B counter high register
Timer B counter low register
Timer B alternate counter high register
Timer B alternate counter low register
Timer B input capture 2 high register
Timer B input capture 2 low register
Timer B output compare 2 high register
Timer B output compare 2 low register
SCI status register
SCI data register
SCI baud rate register
SCI control register 1
SCI control register 2
SCI extended receive prescaler register
Reserved area
SCI extended transmit prescaler register
Control/status register
Data high register
Data low register
Reserved area (24 bytes)
Reserved area (13 bytes)
Register name
Reset status
x000 0000b
xxxx x0xxb
FCh
FCh
C0h
FFh
FFh
00h
00h
80h
00h
80h
00h
00h
00h
00h
00h
00h
00h
00h
xxh
xxh
xxh
xxh
xxh
---
ST72324Bxx
R/W
R/W
R/W
Read only
Read only
R/W
R/W
Read only
Read only
Read only
Read only
Read only
Read only
R/W
R/W
Read only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read only
Read only
Remarks