ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 72

• Manufacturer Part Number: ST72324BK2
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BK2

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

On-chip peripherals
72/193
Table 39.
Table 40.
6:5 CP[1:0]
3:2
Bit
.
4
1
0
TB[1:0]
Counter prescaler
Name
SMS
OIE
OIF
200000
16000
32000
80000
MCCSR register description (continued)
Time base selection
CPU Clock Prescaler
Slow Mode Select
Time Base control
Oscillator interrupt Enable
Oscillator interrupt Flag
These bits select the CPU clock prescaler which is applied in different slow modes.
Their action is conditioned by the setting of the SMS bit. These two bits are set and
cleared by software:
00: f
01: f
10: f
11: f
This bit is set and cleared by software.
0: Normal mode. f
1: Slow mode. f
See
clock and beeper (MCC/RTC)
These bits select the programmable divider time base. They are set and cleared by
software (see
end of the current period (previously set) to avoid an unwanted time shift. This
allows to use this time base as a real-time clock.
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from Active-halt mode. When this bit is set, calling
the ST7 software HALT instruction enters the Active-halt power saving mode
This bit is set by hardware and cleared by software reading the MCCSR register. It
indicates when set that the main oscillator has reached the selected elapsed time
(TB1:0).
0: Timeout not reached
1: Timeout reached
Caution: The BRES and BSET instructions must not be used on the MCCSR
register to avoid unintentionally clearing the OIF bit.
CPU
CPU
CPU
CPU
Section 8.2: Slow mode
in Slow mode = f
in Slow mode = f
in Slow mode = f
in Slow mode = f
Table
CPU
CPU
is given by CP1, CP0.
40). A modification of the time base is taken into account at the
f
OSC2
= f
20 ms
50 ms
OSC2
4 ms
8 ms
OSC2
OSC2
OSC2
OSC2
= 4 MHz
and
.
for more details.
/2
/4
/8
/16
Section 10.2: Main clock controller with real-time
Time base
Function
f
OSC2
10 ms
25 ms
2 ms
4 ms
= 8 MHz
TB1
ST72324Bxx
0
0
1
1
.
TB0
0
1
0
1