71M6533 Maxim, 71M6533 Datasheet
71M6533
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71M6533 Summary of contents
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... The 71M6533 and 71M6534 add several new features to the Teridian flagship 71M6513 polyphase meters, including an SPI interface, advanced power management with < 1µA sleep current, ...
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... Data RAM (XRAM) .................................................................................................... 16 1.3.5 CE Functional Overview ............................................................................................ 17 1.3.6 Delay Compensation ................................................................................................. 18 1.4 80515 MPU Core .................................................................................................................. 19 1.4.1 Memory Organization and Addressing ....................................................................... 19 1.4.2 Special Function Registers (SFRs) ............................................................................ 21 1.4.3 Generic 80515 Special Function Registers ................................................................ 22 1.4.4 71M6533/71M6534-Specific Special Function Registers ............................................ 25 1.4.5 Instruction Set ........................................................................................................... 26 1.4.6 UARTs ...................................................................................................................... 26 1.4.7 Timers and Counters ................................................................................................. 29 1.4.8 WD Timer (Software Watchdog Timer) ...................................................................... 30 1.4.9 Interrupts ................................................................................................................... 30 1.5 On-Chip Resources ............................................................................................................. 37 1 ...
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... Wake on Timer .......................................................................................................... 66 2.6 Data Flow ............................................................................................................................. 66 2.7 CE/MPU Communication .................................................................................................... 67 3 Application Information ............................................................................................................... 68 3.1 Connection of Sensors (CT, Resistive Shunt) ................................................................... 68 3.2 Distinction between 71M6533/71M6534 and 71M6533G/H/71M6534H Parts ..................... 68 3.3 Connecting 5 V Devices ...................................................................................................... 69 3.4 Temperature Measurement ................................................................................................. 69 3.5 Temperature Compensation ............................................................................................... 69 3.5.1 Temperature Coefficients .......................................................................................... 69 3.5.2 Temperature Compensation for VREF ....................................................................... 71 3.5.3 System Temperature Compensation .......................................................................... 72 3.5.4 Temperature Compensation for the RTC ................................................................... 72 3 ...
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... Accuracy over Temperature..................................................................................... 119 5.7 Package Outline Drawings ............................................................................................... 119 5.7.1 71M6533 (100-Pin LQFP) ........................................................................................ 119 5.7.2 71M6534/6534H (120-Pin LQFP) ............................................................................ 120 5.8 Pinout ................................................................................................................................ 121 5.8.1 71M6533/71M6533G/71M6533H Pinout (100-Pin LQFP) ......................................... 121 5.8.2 71M6534/71M6534H Pinout (120-Pin LQFP) ........................................................... 122 5.9 Pin Descriptions ................................................................................................................ 123 5.9.1 Power and Ground Pins........................................................................................... 123 5.9.2 Analog Pins ............................................................................................................. 123 5.9.3 Digital Pins .............................................................................................................. 124 5 ...
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... Figure 50: Typical Wh Accuracy (0. 200 A, 240 V, Room Temperature), Various Load Angles (Differential Mode, CTs) ................................................................................................................ 118 Figure 51: 71M6533/71M6533G/71M6533H 100-Pin LQFP Package Outline ....................................... 119 Figure 52: 71M6534/6534H 120-Pin LQFP Package Outline ................................................................ 120 Figure 53: Pinout for 71M6533/71M6533G/71M6533H LQFP-100 Package ......................................... 121 Figure 54: Pinout for 71M6534/71M6534H LQFP-120 Package ........................................................... 122 Rev 2 5 ...
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... Table 10: Generic 80515 SFRs - Location and Reset Values ................................................................. 22 Table 11: PSW Bit Functions (SFR 0xD0) ............................................................................................... 23 Table 12: Port Registers ........................................................................................................................ 24 Table 13: Stretch Memory Cycle Width .................................................................................................. 25 Table 14: 71M6533/71M6534 Specific SFRs ......................................................................................... 25 Table 16: UART Modes ......................................................................................................................... 27 Table 18: The S1CON (UART1) Register (SFR 0x9B) ............................................................................. 28 Table 19: PCON Register Bit Description (SFR 0x87) ............................................................................. 28 Table 20: Timers/Counters Mode Description ...
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Table 68: Recommended External Components .................................................................................. 108 Table 69: Recommended Operating Conditions ................................................................................... 108 Table 70: Input Logic Levels ................................................................................................................ 109 Table 71: Output Logic Levels ............................................................................................................. 109 Table 72: Power-fault Comparator Performance Specifications ............................................................ 109 Table 73: V2 Comparator ...
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VREF IAP IAN VA IBP VBIAS IBN VB VADC MUX ICP ICN VC VREF VBAT TEMP 2.5V_NV MCK PLL RTCLK (32KHz) OSC XIN MPU_DIV (32 kHz) CKOUT_E XOUT RTCA_ADJ RTC 2.5V_NV RST_SUBSEC QREG,PREG RTC_DAY ...
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... Figure 1. 1.2 Analog Front End (AFE) The AFE of the 71M6533/71M6534 consists of an input multiplexer, a delta-sigma A/D converter and a voltage reference. 1.2.1 Signal Input Pins All analog signal input pins are sensitive to voltage. The VA, VB, and VC pins are single-ended. Pins IAP/IAN, IBP/IBN, ICP/ICN, and IDP/IDN can be programmed individually to be differential or single-ended. ...
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Input Multiplexer The input multiplexer applies the input signals from the pins IAP/IAN, VA, IBP/IBN, VB, ICP/ICN, VC, and IDP/IDN to the input of the ADC. Additionally, using the alternate multiplexer selection, it has the ability to select temperature ...
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... CK32 cycles. The number of CK32 cycles is determined by FIR_LEN[1:0]. 1.2.3 A/D Converter (ADC) A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6533/71M6534. The resolution of the ADC is programmable using the I/O RAM bits M40MHZ and M26MHZ (see CE code must be tailored for use with the selected ADC resolution. ...
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Address Signal Number (HEX) 0 0x00 1 0x01 2 0x02 3 0x03 4 0x04 1.2.5 Voltage References The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The reference is trimmed in production to minimize errors caused ...
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... The internal bias voltage, VBIAS (typically 1.6 V), is used by the ADC as a reference when measuring the temperature and battery monitor signals. 1.2.6 Temperature Sensor The 71M6533 and 71M6534 include an on-chip temperature sensor implemented as a bandgap reference used to determine the die temperature. The MPU may request an alternate multiplexer cycle containing the temperature sensor output by asserting MUX_ALT. ...
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IAP IAN VA IBP IBN VB ICP ICN VBAT TEMP 1.3 Digital Computation Engine (CE) The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately measure energy. The CE ...
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... XFER_BUSY interrupt when the accumulation is complete. 1.3.1 Meter Equations The 71M6533 and 71M6534 provide hardware assistance to the CE in order to support various meter equations. This assistance is controlled through the I/O RAM field EQU[2:0] (equation assist). The Compute Engine (CE) firmware for industrial configurations can implement the equations listed in EQU[2:0] specifies the equation to be used based on the meter configuration and on the number of phases used for metering ...
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... RTM output format. RTM is low when not in use. 1.3.3 Pulse Generators The 71M6533 and 71M6534 provide four pulse generators, RPULSE, WPULSE, XPULSE and YPULSE, as well as hardware support for the RPULSE and WPULSE pulse generators. The pulse generators can be used to output CE status indicators, SAG for example, to DIO pins. ...
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The Data RAM is 32 bits wide and uses an external multiplexer appear byte-wide to the MPU. The Data RAM hardware will convert an MPU byte write operation into a read-modify-write operation that requires two Data RAM ...
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PRE_SAMPS[1: and SUM_CYCLES[5:0] = 50, Figure 6 consisting of 2100 samples of 397µs each, followed by the XFER_BUSY interrupt. The sampling in this example is applied signal. ...
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... MPU External Data Memory (XRAM) Both internal and external memory is physically located on the 71M6533/71M6534 device. The external memory referred to in this documentation is only external to the 80515 MPU core RAM starting at address 0x0000 is shared by the CE and MPU. The CE normally uses the first 1 KB, leaving 3 KB for the MPU ...
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... If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is disabled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0] ≠ 0 because the 71M6533/71M6534 ADC writes to these locations. Setting MUX_DIV[3: disables the ADC output, preventing the CE from writing the first 0x40 bytes of RAM. ...
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... SFRs specific to the 71M6533/71M6534 are shown in bold print on a gray field. The registers at 0x80, 0x88, 0x90, etc., are bit addressable, all others are byte addressable. See the restrictions for the INTBITS ...
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Bit Hex/ Addressable Bin X000 X001 D8 WDCON D0 PSW C8 T2CON IRCON C0 IEN1 IP1 IEN0 IP0 A0 P2 DIR2 98 S0CON S0BUF 90 P1 DIR1 88 TCON TMOD 1.4.3 Generic 80515 ...
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Address Reset value Name (Hex) (Hex) IEN0 0xA8 0x00 IP0 0xA9 0x00 S0RELL 0xAA 0xD9 P3 0xB0 0xFF IEN1 0xB8 0x00 IP1 0xB9 0x00 S0RELH 0xBA 0x03 S1RELH 0xBB 0x03 PDATA 0xBF 0x00 IRCON 0xC0 0x00 T2CON 0xC8 0x00 PSW ...
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... The CKCON[2:0] field defines the stretch memory cycles that are used for MOVX instructions when accessing external peripherals. The practical value of this field for the 71M6533/71M6534 is to guarantee access to XRAM between CE, MPU, and SPI. The default setting of CKCON[2:0] (001) should not be changed ...
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... Stretch CKCON[2:0] 000 001 010 011 100 101 110 111 1.4.4 71M6533/71M6534-Specific Special Function Registers Table 14 shows the location and description of the 71M6533/71M6534-specific SFRs. Table 14: 71M6533/71M6534 Specific SFRs Register SFR (Alternate Name) Address EEDATA 0x9E EECTRL 0x9F ERASE 0x94 (FLSH_ERASE) FL_BANK[2:0] 0xB6[2:0] ...
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... Software User’s Guide (SUG). 1.4.6 UARTs The 71M6533 and 71M6534 include a UART (UART0) that can be programmed to communicate with a variety of AMR modules and other external devices. A second UART (UART1) is connected to the optical port, as described in the 1 ...
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WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps. ...
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Table 17: The S0CON (UART0) Register (SFR 0x98) Bit Symbol Function The SM0 and SM1 bits set the UART0 mode: S0CON[7] SM0 S0CON[6] SM1 S0CON[5] SM20 Enables the inter-processor communication feature. S0CON[4] REN0 If set, enables serial reception. Cleared by ...
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... (T0 and T1 are the timer gating inputs derived from certain DIO pins, see cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock frequency (CKMPU). There are no restrictions on the duty cycle, however to ensure proper recognition of the state, an input should be stable for at least 1 machine cycle ...
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TMOD[5:4] M1:M0 Selects the mode for Timer/Counter 1 as shown in Timer/Counter 0 If TMOD[3] is set, external input signal control is enabled for Counter 0. external gate control. The TR0 bit in the TCON register (SFR 0x88) must ...
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RETI. When an RETI is performed, the processor will return to the instruction that would have been next when the interrupt occurred. When the interrupt condition occurs, the processor will also indicate this ...
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Table 27: TCON Bit Functions (SFR 0x88) Bit Symbol Function TCON[7] TF1 Timer 1 overflow flag. TCON[6] TR1 Not used for interrupt control. TCON[5] TF0 Timer 0 overflow flag. TCON[4] TR0 Not used for interrupt control. TCON[3] IE1 External interrupt ...
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... External MPU Interrupts The seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 71M6533/71M6534, for example the CE, DIO, RTC, EEPROM interface. The external interrupts are connected as shown in programmable in the MPU via the I3FR and I2FR bits in T2CON. Interrupts 2 and 3 should be programmed for falling sensitivity (I3FR = I2FR = 0) ...
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Interrupt Enable Name Location EX_XFER 2002[0] EX_RTC 2002[1] IEN_WD_NROVF 20B0[0] IEN_SPI 20B0[4] EX_FWCOL 2007[4] EX_PLL 2007[5] † The AUTOWAKE and PB flag bits are shown in even though they are not actually related to an interrupt. These bits are set ...
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Table 34: Interrupt Priority Registers (IP0 and IP1) Register Address Bit 7 (MSB) – IP0 SFR 0xA9 – IP1 SFR 0xB9 Interrupt Sources and Vectors Table 36 shows the interrupts with their associated flags and vector addresses. Interrupt Request Flag ...
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... Data Sheet ...
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... On-Chip Resources 1.5.1 Oscillator The 71M6533/71M6534 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do not require a high-current oscillator circuit. The oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. The oscillator power dissipation is very low to maximize the lifetime of any battery attached to VBAT ...
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... MPU firmware can treat them as a single register. A single binary number can be calculated and then loaded into them at the same time. The 71M6533 and 71M6534 have two rate adjustment mechanisms. The first is an analog rate adjustment, using RTCA_ADJ[6:0], which trims the crystal load capacitance. Setting RTCA_ADJ[6: minimizes the load capacitance, maximizing the oscillator frequency ...
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... Physical Memory Flash Memory The device includes 128 KB (71M6533/H, 71M6534) or 256 KB (71M6533G, 71M6534H) of on-chip flash memory. The flash memory primarily contains MPU and CE program code. It also contains images of the CE and MPU data in RAM as well as of I/O RAM. On power-up, before enabling the CE, the MPU copies these images to their respective locations ...
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The flash memory is segmented into individually erasable pages that contain 1024 bytes. Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must begin boundary of the ...
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... Writes to page zero, whether by MPU or ICE are inhibited. MPU/CE RAM The 71M6533 and 71M6534 includes static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in the MPU core. The static RAM are used for data storage for both MPU and CE operations. ...
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... UART1. This function is controlled with the UMUX_E and UMUX_SEL bits in I/O RAM. 1.5.7 Digital I/O The device includes pins (71M6533 pins (71M6534) of general purpose digital I/O. These pins are compatible with 5 V inputs (no current limiting resistors are needed). The Digital I/O pins can be categorized as follows: • ...
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... Data Register – 1 Direction Register 0 = input output Internal Resources Y Y Configurable Table 40: Data/Direction Registers and Internal Resources for DIO 16-30 DIO 16 17 LCD Segment 36 37 71M6533 Pin # 33 12 71M6534 Pin # Configuration (DIO or LCD segment) LCD_BITMAP[39:32 Data Register 0 1 Direction Register ...
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... Direction Register – – input output Table 42: Data/Direction and Internal Resources for DIO 48-58 DIO LCD Segment 71M6533 Pin # 71M6534 Pin # Configuration (DIO or LCD segment) Data Register Direction Register 0 = input output See the tables in the I/O RAM Description DIO43 is controlled by LCD_SEG63[0] which resolves to I/O RAM location 0x2045[4]. ...
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Since the control for DIO_24 through DIO_55 is shared with the control for LCD segments, the firmware must take care not to disturb the DIO pins when accessing the LCD segments and vice versa. Usually, this requires reading the I/O ...
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... LCD display with 25% duty cycle. At eight pixels per digit, this corresponds to 7 digits for the 71M6533 or 7 digits for the 71M6534. The LCD interface is flexible and can drive 7-segment digits, 14- segments digits or enunciator symbols. ...
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... ADC LSB size and the conversion accuracy. 1.5.10 EEPROM Interface The 71M6533 and 71M6534 provides hardware support for either a two-pin or a three-wire (µ-wire) type of EEPROM interface. The interfaces use the EECTRL and EEDATA registers for communication. Two-pin EEPROM Interface The dedicated 2-pin serial interface communicates with external EEPROM devices ...
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Status Read/ Name Bit Write The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. In this case, a resistor has to be used in series with SDA to avoid data collisions due to limits ...
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EECTRL Byte Written Write -- No HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) Figure 10: 3-wire Interface. Write Command, HiZ=0. EECTRL Byte Written Write -- With HiZ SCLK (output) SDATA (output) SDATA output Z BUSY (bit) Figure ...
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... Possible applications for the SPI interface are external host reads data from CE locations to obtain metering information. This can be used in applications where the 71M6533 or 71M6534 function as a smart front-end with preprocessing capability. Since the addresses are in 16-bit format, any type of XRAM data can be accessed: CE, MPU, I/O RAM, but not SFRs or the 80515-internal register bank ...
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The SPI_FLAG flag bit will be set upon every SPI transaction regardless of whether the command is 11xx xxxx or 10xx xxxx. The SP_ADDR[15:0] bit field is for writing purposes by the host only. Data read from SP_ADDR[15:0] will not ...
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MPU can access the bus. There are no issues with Data RAM access; SPI and the MPU will share the bus with no conflicts for Data RAM access. Table 48: I/O RAM Registers Accessible via SPI Name ...
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... MPU has to be used for read and write operations involving the SFRs. 1.5.12 Hardware Watchdog Timer An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6533/71M6534. It uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every 1 ...
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If enabled with the IEN_WD_NROVF bit in I/O RAM, an interrupt occurs roughly 1 ms before the WDT resets the chip. This can be used to determine the cause of a WDT reset since it allows the code to log ...
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... For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state electricity meter IC such as the Teridian 71M6533 and 71M6534 functions by emulating the integral operation above, i.e. it processes current and voltage samples through an ADC at a constant frequency. As long as ...
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System Timing Summary Figure 19 summarizes the timing relationships between the input MUX states, the CE_BUSY signal and the two serial output streams. In this example, MUX_DIV[3: and FIR_LEN[1: The duration of each MUX frame ...
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... PLL is stable. This mode is the normal operation mode where the part is capable of measuring energy. When system power is not available (i.e. when V1<VBIAS), the 71M6533 and 71M6534 will be in one of three battery modes: BROWNOUT, LCD, or SLEEP mode. ...
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... SLEEP mode (BAT_OK false). The battery voltage must stay above ensure that BAT_OK remains true. Under this condition, the 71M6533 and 71M6534 stays in SLEEP mode, even if the voltage margin for the LDO improves (BAT_OK true). ...
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BROWNOUT Mode In BROWNOUT mode, most non-metering digital functions are active (as shown in ICE, UART, EEPROM, LCD and RTC. In BROWNOUT mode, a low-bias current regulator will provide 2.5 Volts to V2P5 and V2P5NV. The regulator has an ...
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System (V3P3SYS) V1_OK Battery Current BROWNOUT MPU Mode WAKE MPU Clock Source PLL_OK Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns V3P3SYS and VBAT V1_OK Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal RESETZ ...
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VBAT Battery Current MPU Mode MPU Clock Source WAKE PLL_OK Internal RESETZ VBAT_OK Figure 24: Power-Up Timing with VBAT Only Rev 2 BROWNOUT Xtal 14.5 CK32 cycles 1024 CK32 cycles time 61 ...
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VREF IAP IAN VA VBIAS IBP IBN VB VADC MUX ICP ICN VC VREF VBAT TEMP 2.5V_NV MCK RTCLK (32KHz) OSC XIN MPU_DIV (32 kHz) CKOUT_E XOUT RTCA_ADJ RTC 2.5V_NV RST_SUBSEC QREG,PREG RTC_DAY RTC_DATE ...
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VREF IAP IAN VA VBIAS IBP IBN VB VADC MUX ICP ICN VC VREF VBAT TEMP 2.5V_NV MCK RTCLK (32KHz) OSC XIN MPU_DIV (32 kHz) CKOUT_E XOUT RTCA_ADJ RTC 2.5V_NV RST_SUBSEC QREG,PREG RTC_DAY RTC_DATE ...
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VREF IAP IAN VA IBP VBIAS IBN VB VADC MUX ICP ICN VC VREF IDP IDN VBAT TEMP MCK PLL RTCLK ( 32 KHz ) OSC XIN MPU _ DIV ( 32 kHz ) ...
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... MPU will begin executing in BROWNOUT mode, starting at address 00. 2.4.2 Power Fault Circuit The 71M6533 and 71M6534 include a comparator to monitor system power fault conditions. When the output of the comparator falls (V1<VBIAS), the I/O RAM PLL_OK bit is zeroed and the part switches to BROWNOUT mode battery is present (and the MPU keeps executing code battery is not present, as indicated by BAT_OK=0, WAKE will fall and the part will enter SLEEP mode ...
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System Power (V3P3SYS wake- up timer WAKE LCD MPU Mode PLL_OK 2.5.2 Wake on Timer If the part is in SLEEP or LCD mode, it can be awakened by the wake-up timer. Until this timer times out, the ...
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CE/MPU Communication Figure 30 shows the functional relationships between the CE and the MPU. The CE is controlled by the MPU via shared registers in the I/O RAM and in RAM. The CE outputs two interrupt signals to the ...
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... Note: Ferrites or other inductive components must not be connected directly to the sensor input pins (InP, InN Vn). 3.2 Distinction between 71M6533/71M6534 and 71M6533G/H/71M6534H Parts The 71M6533G, 71M6533H, and 71M6534H (high-accuracy) parts go through an additional process of characterization during production which makes them suitable to high-accuracy performance over temperature. ...
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... The factor TRIMT used to calculate PPMC is derived from the trim fuse TRIMT[7:0]. 3.3 Connecting 5 V Devices All digital input pins of the 71M6533/71M6534 are compatible with external 5 V devices. I/O pins configured as inputs do not require current-limiting resistors when they are connected to external 5 V devices. ...
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... If the reference voltage is used to measure both voltage and current, the identical errors of ±0.252% add maximum Wh registration error of ±0.504%. The maximum deviation of ±945 PPM (or 0.0945%) for the high-accuracy parts is reached at the temperature extremes. If the reference voltage is used to measure both voltage and current, the identical errors of ± ...
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Error Band (PPM) over Temperature (°C) 2800 2400 2000 1600 1200 800 400 0 -400 -800 -1200 -1600 -2000 -2400 -2800 -40 Figure 34: Error Band for VREF over Temperature (Regular-Accuracy Parts) Error Band (PPM) over Temperature (°C) 1200 800 ...
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... System Temperature Compensation In a production electricity meter, the 71M6533 and 71M6534 is not the only component contributing to temperature dependency. A whole range of components (e.g. current transformers, resistor dividers, power sources, filter capacitors) will contribute temperature effects. Since the output of the on-chip temperature sensor is accessible to the MPU, temperature compensation mechanisms with great flexibility are possible ...
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... The CS and CLK pins should be pulled down with a resistor to prevent operation of the three-wire device on power-up, before the 71M6533/71M6534 can establish a stable signal for CS and CLK. • The DIO_EEX[1:0] field in I/O RAM must be set order to convert the DIO pins DIO4 and DIO5 to µ ...
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... The UART0 RX pin should be pulled down kΩ resistor and additionally protected by a 100 pF ceramic capacitor, as shown in Figure 39. 71M6533/71M6534 4.6 Optical Interface (UART1) The OPT_TX and OPT_RX pins can be used for a regular serial interface (by connecting a RS_232 transceiver for example), or they can be used to directly operate optical components (for example, an infrared diode and phototransistor implementing a FLAG interface) ...
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... For a production meter, the RESET pin should be protected by the by the external components shown in Figure 42, right side. R1 should be in the range of 100 Ω and mounted as closely as possible to the IC. Since the 71M6533 and 71M6534 generates its own power-on reset, a reset button or circuitry, as shown in Figure 42, is only required for test units and prototypes ...
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... VBAT pin. 76 71M6533/ V3P3D 71M6534 RESET 10k ? R 1 GNDD 43. Production boards should have the ICE_E pin connected to ground LCD Segments (optional) 71M6533/71M6534 44. During the battery test, a DIO pin is activated as an output and 71M6533/ 71M6534 ICE_E E_RST E_RXT E_TCLK Rev 2 ...
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... All application-specific MPU functions mentioned in Teridian demonstration source code. The code is available as part of the Demonstration Kit for the 71M6533/71M6534. The Demonstration Kits come with the 71M6533/71M6534 preprogrammed with demo firmware and mounted on a functional sample meter Demo Board. The Demo Boards allow for quick and efficient evaluation of the IC without having to write firmware or having to supply an in-circuit emulator (ICE) ...
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... Meter Calibration Once the Teridian 71M6533 and 71M6534 energy meter device has been installed in a meter system, it must be calibrated. A complete calibration includes the following: • Calibration of the metrology section, i.e. calibration for tolerances of the current sensors, voltage dividers and signal conditioning components as well as of the internal reference voltage (VREF). ...
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... BOOT_SIZE[7:0] CE_LCTN[7:0] LCD_ONLY WAKE_RES (0000) SEL_IBN CHOP_IB U SEL_IDN CHOP_ID U INT6 INT5 INT4 IE_WAKE IE_PB IE_FWCOL1 71M6533/G/H and 71M6534/H Data Sheet † ) apply to the 71M6534 only. Bit 3 Bit 2 Bit 1 CE10MHZ U SUM_CYCLES[5:0] RTM_E WD_OVF EX_RTC VREF_DIS MPU_DIV[2:0] ADC_E MUX_ALT U FIR_LEN[1:0] ...
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... Data Sheet Name Address Bit 7 Digital I/O: 20AF U DIO0 DIO_EEX[1:0] 2008 DIO1 2009 U DIO2 200A U DIO3 200B U DIO4 200C U DIO5 200D U DIO6 200E U R (00) 200F † UMUX_E UMUX_SEL DIO7/ P0 SFR 80 DIO8 SFR A2 DIO9 / P1 DIO_1[7:5] SFR 90 (Port 1) DIO10 SFR 91 DIO_DIR1[7:5] ...
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... RTC write protect register (write data is discarded) BME R (0) R (0) LCD_E LCD_MODE[2:0] Table 54: I/O RAM Description – Alphabetical Table 54: I/O RAM Description – Alphabetical U RTM0[7:0] U RTM1[7:0] U RTM2[7:0] U RTM3[7:0] 71M6533/G/H and 71M6534/H Data Sheet Bit 3 Bit 2 Bit 1 RTC_SEC[5:0] RTC_MIN[5:0] RTC_HR[4:0] U RTC_DAY[2:0] RTC_DATE[2:0] RTC_MO[3:0] U PREG[16:14] QREG[1: ...
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... Data Sheet Name Address Bit 7 SPI Interface: SPI… SPE 2070 SP_CMD 2071 SP_ADH 2072 SP_ADL 2073 Pulse Generator: PLS_W 2080 PLS_I 2081 ADC Mux: SLOT0 2090 SLOT1 2091 SLOT2 2092 SLOT3 2093 SLOT4 2094 SLOT5 2096 SLOT6 ...
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... MUX frame is inserted When CHOP_I_EN is set, chop mode for the analog current inputs can be enabled R/W 0 with the CHOP_IA, CHOP_IB, CHOP_IC, and CHOP_ID bits R/W When CHOP_I_EN is set, these bits enable chop mode for the respective channel 71M6533/G/H and 71M6534/H Data Sheet 83 ...
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... Data Sheet CKOUT_E 2004[ COMPSTAT 2003[0] DI_RPB[2:0] 2009[2:0] 0 DIO_R1[2:0] 2009[6:4] 0 DIO_R2[2:0] 200A[2:0] 0 DIO_R3[6:4] 200A[6:4] 0 DIO_R4[2:0] 200B[2:0] 0 DIO_R5[2:0] 200B[6:4] 0 DIO_R6[2:0] 200C[2:0] 0 DIO_R7[2:0] 200C[6:4] 0 DIO_R8[2:0] 200D[2:0] 0 DIO_R9[2:0] 200D[6:4] 0 DIO_R10[2:0] 200E[2:0] 0 DIO_R11[2:0] 200E[6:4] 0 DIO_RRX[2:0]* 20AF[2:0] 0 DIO_DIR0[7:1] SFR A2[7:1] 0 DIO_DIR1[7:5, 3:0], SFR 91 0 † ...
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... Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, the FirmWareCollision (FWCOL), and PLL interrupts. Note that if one of these interrupts enabled, its corresponding MPU EX enable must also be set. See 0 Interrupts for details. 0 71M6533/G/H and 71M6534/H Data Sheet Section 1.4.9 85 ...
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... Data Sheet FIR_LEN[1:0] 2007[3:2] 1 FL_BANK[1:0] SFR B6[1:0] 1 † FL_BANK[2:0] SFR B6[2:0] FLSH_ERASE SFR 94[7:0] 0 [7:0] FLSH_MEEN SFR B2[1] 0 FLSH_PGADR SFR B7 [7:2] 0 [5:0] FLSH_PWE SFR B2[0] 0 FOVRIDE 20FD[ FIR_LEN[1:0] controls the length of the ADC decimation FIR filter. [M40MHZ, M26MHZ] FIR_LEN[1:0] [00], [10], or [11] 1 R/W [01] Flash bank selection. Flash memory above mapped to the MPU address space from 0x8000 to 0xFFFF banks ...
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... DIO22/SEG42, is only applicable to the 71M6534. Unused bits should L R/W be set to zero LCD pin DIO pin. Configuration for DIO30/SEG50 through DIO28/SEG48. LCD_BITMAP[48], corresponding to DIO28/SEG48, is only applicable to the 71M6534. Unused bits should L R/W be set to zero LCD pin DIO pin. 71M6533/G/H and 71M6534/H Data Sheet Flash Memory section for 87 ...
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... Data Sheet LCD_BITMAP [63:61], 2027[7:5,3:0] 0 † [59:56] LCD_BITMAP 2028[7:0] 0 [71:64] LCD_BLKMAP18 205A[3:0] 0 [3:0] LCD_CLK[1:0] 2021[1:0] 0 LCD_DAC[2:0] 20AB[3:1] 0 LCD_E 2021[5] 0 LCD_MODE[2:0] 2021[4: Configuration for DIO43/SEG63 through DIO41/SEG61 and DIO39/SEG59 through DIO36/SEG56. LCD_BITMAP[62], corresponding to DIO42/SEG62, and LCD_BITMAP[59:56] ,corresponding to DIO39/SEG59 through DIO36/SEG56, are only ...
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... LCD_SEG75[3:0] 2051[7:4] 0 Rev 2 Puts the 71M6533/71M6534 to sleep, but with the LCD display still active. LCD_ONLY is ignored if system power is present. While in SLEEP mode, the device will wake reset, when the autowake timer times out, when the push button is pushed, or when system power returns ...
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... Data Sheet LCD_Y 2021[6] 0 M26MHZ 2005[4] 0 M40MHZ 2005[0] 0 MPU_DIV[2:0] 2004[2:0] 0 MUX_ALT 2005[2] 0 MUX_DIV[3:0] 209D[3:0] 0 MUX_SYNC_E 2020[7] 0 OPT_FDC[1:0] 2007[1: LCD Blink Frequency (ignored if blink is disabled or if the segment is off (500 ms ON, 500 ms OFF 0 ON OFF) M26MHZ and M40MHZ set the master clock (MCK) frequency ...
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... PREG[16:0] and QREG[1:0] are separate in hardware but can be programmed with a NV R/W single number calculated by the MPU. . PREG[16:0] and QREG[1:0] are non-volatile, but have no correcting function in SLEEP mode. The duration of the pre-summer, in samples. PRE_SAMPS[1:0] Pre-Summer Duration 71M6533/G/H and 71M6534/H Data Sheet . Where T is PLS_INTERVAL for additional details 100 91 ...
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... PREBOOT is set. SECURE is cleared when the flash is mass-erased and on chip reset. The bit may only be set, attempts to write zero are ignored. Puts the 71M6533/71M6534 into SLEEP mode. This bit is ignored if system power is present. The 71M6533 and 71M6534 will wake when the autowake timer times out, ...
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... Selects one of 32 signals for TMUXOUT. For details, see Section – R/W (TMUXOUT Pin). Contains TRIMT[7:0], TRIMBGA,TRIMBGB or TRIMM[2:0] depending on the value written to TRIMSEL[3:0]. If TRIMBGB = 0, the device is a 71M6533/71M6534, else R/W a 71M6533H/71M6534H. Selects the temperature trim fuse to be read with the TRIM register: TRIMSEL[3:0] ...
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... Data Sheet – 2006 VERSION[7:0] – 20C8 VREF_CAL 2004[7] 0 VREF_DIS 2004[3] 0 WAKE_ARM 20A9[7] 0 WAKE_PRD 20A9[2:0] 001 WAKE_RES 20A9[3] 0 WD_NROVF_ 20B1[0] – FLAG WD_RST SFR F8[7] 0 WD_OVF 2002[ 201F[7:0] WRPROT_BT SFR B2[5] 0 WRPROT_CE SFR B2[4] 0 † Applicable to the 71M6534 only. 94 The device version index. This word may be read by the firmware to determine the – ...
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... Other variations of the CE code may be available. The description in this section applies to CE code revision CE34A02D, which functions for both the 71M6533 and the 71M6534. This version of the CE code does not process the ID current channel. Also available are CE codes capable of calculating and measuring the ID channel ...
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Environment Before starting the CE using the CE_E bit, the MPU has to establish the proper environment for the CE by implementing the following steps: • Load the CE data into RAM. • Establish the equation to be applied ...
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CE Calculations Table 55: CE EQU[2:0] Equations and Element Input Mapping Watt & VAR Element Input Mapping Formula EQU[ 2:0] (WSUM/VARS W0SUM/ VAR0SUM UM element, 2W 1φ) VA*(IA-IB)/ element, 3W 1φ) VA*IA + ...
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CE Status and Control CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. It contains sag warning flags for phase ...
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... When EXT_TEMP = 1 (external compensation), the MPU is allowed to control the CE gain using GAIN_ADJ, based on any algorithm implemented in MPU code. The 71M6533 Demo Code creep function halts both internal and external pulse generation. The FREQSEL1 and FREQSEL0 bits select the phase used to control the CE-internal PLL. CE accuracy depends on the channel selected by the FREQSEL1 and FREQSEL0 bits receiving a clean voltage signal ...
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PULSE_FAST [1] PULSE_SLOW [0] Table 59: Sag Threshold and Gain Adjust Control CE Name Address SAG_THR 0x24 2.39*10 GAIN_ADJ 0x40 5.3.8 CE Transfer Variables When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the ...
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WSUM_X and VARSUM_X are the signed sum of Phase-A, Phase-B and Phase VARh values according to the metering equation specified in the I/O RAM register EQU[2:0]. WxSUM_X is the Wh value accumulated for phase x in the last ...
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CE Name Address FREQ_X 0x82 0x97 PH_AtoB_X PH_AtoC_X 0x98 MAINEDGE_X 0x83 VBAT_SUM_X 0x84 5.3.9 Temperature Measurement and Temperature Compensation Table 63 describes the CE registers supporting temperature measurement and temperature compensation. CE Name Default Address TEMP_RAW 0x81 TEMP_X 0x9D 0x39 ...
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... PULSE_WIDTH allows adjustment of the pulse width for compatibility with calibration and other external equipment. The minimum pulse width possible is 66.16µs. The maximum time jitter is1/6 of the MUX cycle period (nominally 67 µs) and is independent of the number of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is 67 ppm. ...
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Noise Suppression and Version Parameters Table 65 shows the CE parameters used for suppression of noise due to scaling and truncation effects. Table 65: CE Parameters for Noise Suppression and Code Version CE Name Default Address QUANTA 0x26 QUANTB ...
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CE Flow Diagrams Figure 45 through Figure 47 show the data flow through the CE in simplified form. Functions not shown include delay compensation, sample interpolation, scaling and the processing of meter equations. multiplexer ...
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VARA VARB VARC PRE_SAMPS SQUARE Figure 47: CE Data Flow: Squaring and Summation Stages 106 SUM WASUM_X WBSUM_X Σ WCSUM_X VARASUM_X VARBSUM_X VARCSUM_X Σ SUM_CYCLES=60 & ...
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... Absolute Maximum Ratings Table 67 shows the absolute maximum ranges for the device. Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions not implied ...
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Recommended External Components Table 68: Recommended External Components Name From To C1 V3P3A AGND C2 V3P3D GNDD CSYS V3P3SYS GNDD C2P5 V2P5 GNDD XTAL XIN XOUT CXS XIN AGND CXL XOUT AGND Notes: 1. AGND and GNDD should be ...
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Performance Specifications 6.4.1 Input Logic Levels Parameter † Digital high-level input voltage † Digital low-level input voltage , V Input pull-up current E_RXTX, E_ISYNC E_RST, CKTEST Other digital inputs Input pull down current ICE_E RESET ...
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... On resistance – V3P3SYS to V3P3D On resistance – VBAT to V3P3D 110 Condition FIR_LEN=0 (L=138) FIR_LEN=1 (L=288) FIR_LEN=2 (L=384) FIR_LEN=0 (L=186) FIR_LEN=1 (L=384) FIR_LEN=2 (L=588) Condition BROWNOUT mode 71M6533/6533H 71M6534H LCD Mode LCD DAC off LCD DAC on SLEEP Mode Condition | I | ≤ V3P3D | I | ≤ ...
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... Parameter V2P5 V2P5 load regulation VBAT voltage requirement PSRR ΔV2P5/ΔVBAT 6.4.10 Crystal Oscillator Table 79: Crystal Oscillator Performance Specifications Parameter Maximum Output Power to Crystal 2 XIN to XOUT Capacitance 2 Capacitance to GNDD XIN XOUT 1 This specification defines a nominal relationship rather than a measured parameter. Correct circuit operation will be verified with other specs that use this nominal relationship as a reference ...
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... VLC0 Voltage , ⅓ bias VLC1 Impedance VLC0 Impedance † VLCD is V3P3SYS in MISSION mode and VBAT in BROWNOUT and LCD modes. †† Specified as percentage of VLC2, the maximum LCD voltage. 112 Condition 1 ≤ LCD_DAC ≤ 7 DAC ) − 019 V Condition † ...
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Temperature Sensor Table 83 shows the performance for the temperature sensor. The LSB values do not include the 8-bit left shift at CE input. Table 83: Temperature Sensor Performance Specifications Parameter Nominal relationship: N( [M40MHZ, M26MH] ...
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... VNOM temperature coefficients TC1 TC2 VREF(T) deviation from VNOM(T) 6 VREF ( T ) − VNOM ( VNOM ( T ) max( T − TRIMBGA and TRIMBGB are not available (71M6533, 71M6534) VNOM temperature coefficients: TC1 TC2 VREF(T) deviation from VNOM(T) VREF T VNOM − VNOM ( T ) max( T − 22 ...
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ADC Converter, V3P3A Referenced Table 85 shows the performance specifications for the ADC converter, V3P3A referenced. For this data, FIR_LEN=2, [M40MHZ, M26MHZ]=[00], unless stated otherwise, VREF_DIS=0. LSB values do not include the 8-bit left shift at the CE input. ...
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Timing Specifications 6.5.1 Flash Memory Table 86: Flash Memory Timing Specifications Parameter Flash Read Pulse Width Flash write cycles Flash data retention Flash data retention Flash byte writes between page or mass erase operations Write Time per Byte Page ...
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SPI Slave Port (MISSION Mode) Table 90: SPI Slave Port (MISSION Mode) Timing Parameter t PCLK cycle time SPIcyc t Enable lead time SPILead t Enable lag time SPILag t PCLK pulse width: SPIW High Low t PCSZ to ...
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... Wh Performance, Equation 5, 45 Hz 240 V - 0° Phase 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 Figure 49: Wh Accuracy (0 200 A, 240 V, Room Temperature) at Various Frequencies 71M6533/6534 Wh Accuracy at Various Phase Angles 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0.01 0.1 Figure 50: Typical Wh Accuracy (0. 200 A, 240 V, Room Temperature), Various Load Angles 118 ...
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... Accuracy over Temperature With digital temperature compensation enabled, the temperature characteristics of the reference voltage (VREF) are compensated to within ±40 PPM/°C for the 71M6533/71M6534 and within ±15 PPM/°C for the 71M6533H/71M6534H. 6.7 Package Outline Drawings 6.7.1 71M6533 (100-Pin LQFP) Controlling dimensions are in mm. ...
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LQFP) Controlling dimensions are in mm. 7.000 120 1 13.950 +/- 0.100 0.180 +/- 0.050 Figure 52: 71M6534/6534H 120-Pin LQFP Package Outline 120 16.000 +/- 0.200 14.000 +/- 0.100 8.000 MAX. 1.600 1.400 +/- 0.050 0.400 0.100 ...
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... SEG4/PSDO 10 SEG5/PCSZ 11 SEG37/DIO17 12 SEG38/DIO18/MTX 13 DIO56 14 DIO57 15 DIO58 16 DIO3 17 COM0 18 COM1 19 COM2 20 COM3 21 SEG67/DIO47 22 SEG68/DIO48 23 SEG69/DIO49 24 SEG70/DIO50 25 Figure 53: Pinout for 71M6533/71M6533G/71M6533H LQFP-100 Package Rev 2 TERIDIAN 71M6533 71M6533G 71M6533H GNDD 75 RESET 74 V2P5 73 VBAT SEG31/DIO11 70 SEG30/DIO10 69 SEG29/DIO9/YPULSE 68 SEG28/DIO8/XPULSE 67 SEG41/DIO21 66 SEG40/DIO20 65 SEG39/DIO19 64 SEG27/DIO7/RPULSE 63 SEG26/DIO6/WPULSE ...
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Pinout (120-Pin LQFP) GNDD 1 SEG9/E_RXTX 2 DIO2/OPT_TX 3 TMUXOUT 4 SEG66/DIO46 SEG3/PCLK 7 V3P3D 8 SEG19/CKTEST 9 V3P3SYS 10 SEG4/PSDO 11 SEG5/PCSZ 12 SEG54/E_TBUS3 13 SEG53/E_TBUS2 14 SEG52/E_TBUS1 15 SEG51/E_TBUS0 16 SEG37/DIO17 17 SEG38/DIO18/MTX ...
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Pin Descriptions Pins marked with an asterisk (e.g. V2*) are only available on the 71M6534. 6.9.1 Power and Ground Pins Name Type Circuit Description – GNDA P Analog ground: This pin should be connected directly to the ground plane. ...
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Digital Pins Name Type Circuit Description COM3,COM2 COM1,COM0 SEG0…SEG2, SEG8 SEG12…SEG18, SEG20…SEG23 SEG24/DIO4 … SEG31/DIO11, SEG32/DIO12* SEG33/DIO13 … SEG41/DIO21, SEG42/DIO22* SEG43/DIO23 … SEG47/DIO27, SEG48/DIO28* SEG49/DIO29, SEG50/DIO30, SEG56/DIO36* I … SEG59/DIO39* SEG61/DIO41, SEG62/DIO42* ...
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E_RXTX/SEG9 I E_RST/SEG11 I E_TCLK/SEG10 ICE_E I 2 CKTEST/SEG19 MUXSYNC/SEG7 TMUXOUT O 4 OPT_RX/DIO1 I OPT_TX/DIO2 I RESET ...
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I/O Equivalent Circuits V3P3D V3P3D 110K Digital CMOS Input Input Pin GNDD Digital Input Equivalent Circuit Type 1: Standard Digital Input or pin configured as DIO Input with Internal Pull-Up V3P3D Digital CMOS Input Input Pin 110K GNDD GNDD ...
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... Users must also refer to the following documents related to the 71M6533 and 71M6534: • 71M6533/G/H and 71M6534/H Data Sheet (this document) • 71M653X Software User’s Guide (SUG) 9 Contact Information For more information about Maxim products or to check the availability of the 71M6533/G/H and 71M6534/H, contact technical support at www.maxim-ic.com/support. Rev 2 FLASH SIZE PACKAGE (KB) ± ...
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Appendix A: Acronyms AFE Analog Front End AMR Automatic Meter Reading ANSI American National Standards Institute CE Compute Engine DIO Digital I /O DSP Digital Signal Processor FIR Finite Impulse Response Inter-IC Bus ICE In-Circuit Emulator IEC ...
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Appendix B: Revision History REVISION REVISION NUMBER DATE 2 2/12 1.2 August 3, 2010 Rev 2 DESCRIPTION 1) Added Guaranteed By Design notes to the Electrical Specifications. 2) Added explanation on NV properties of RTCA_ADJ[ ] and PREG/QREG[ ] and ...
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... Added VBAT_SUM_X to 21) Section 5.3.12: Added CAL_ID location. 22) Section 1.1.1: Updated flow diagrams. 23) Added 71M6533G (256 KB). 24) Updated value for capacitor at XOUT (7 pF). 25) Added description of delay compensation in CE (1.3.6). 26) Added description of error bands for VREF in 3.5.1. 27) Replaced Accuracy with Trim Deviation in Ordering Information. ...
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... 2012 Maxim Integrated Products 71M6533/G/H and 71M6534/H Data Sheet DESCRIPTION Changes and corrections: 1) Stated < ...
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Rev 2 ...