71M6533 Maxim, 71M6533 Datasheet - Page 28

• Manufacturer Part Number: 71M6533
• Description: The Teridian™ 71M6533 and 71M6534 are third-generation polyphase metering systems-on-chips (SoCs) with a 10MHz 8051-compatible MPU core, low-power RTC, flash, and LCD driver
• Manufacturer: Maxim

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S0CON[7]
S0CON[6]
S0CON[5]
S0CON[4]
S0CON[3]
S0CON[2]
S0CON[1]
S0CON[0]
S1CON[7]
S1CON[5]
S1CON[4]
S1CON[3]
S1CON[2]
S1CON[1]
S1CON[0]
PCON[7]
PCON[6:2]
PCON[1]
PCON[0]
Bit
Bit
Bit
SM0
SM1
SM20
REN0
TB80
RB80
TI0
RI0
SM
SM21
REN1
TB81
RB81
TI1
RI1
SMOD
–
STOP
IDLE
Symbol
Symbol
Symbol
Table 19: PCON Register Bit Description (SFR 0x87)
Table 18: The S1CON (UART1) Register (SFR 0x9B)
Table 17: The S0CON (UART0) Register (SFR 0x98)
Function
The SM0 and SM1 bits set the UART0 mode:
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,
depending on the function it performs (parity check, multiprocessor
communication etc.)
In Modes 2 and 3 it is the 9
is the stop bit. In mode 0, this bit is not used. Must be cleared by software.
Transmit interrupt flag; set by hardware after completion of a serial transfer.
Must be cleared by software.
Receive interrupt flag; set by hardware after completion of a serial reception.
Must be cleared by software.
Function
Sets the baud rate and mode for UART1.
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9
on the function it performs (parity check, multiprocessor communication
etc.)
In Modes A and B, it is the 9
RB81 is the stop bit. Must be cleared by software
Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
Function
The SMOD bit doubles the baud rate when set
Not used.
Stops MPU flash access and MPU peripherals including timers and UARTs
when set until an external interrupt is received.
Stops MPU flash access when set until an internal interrupt is received.
th
SM
Mode
0
1
transmitted data bit in Mode A. Set or cleared by the MPU, depending
0
1
2
3
Mode
A
B
N/A
8-bit UART
9-bit UART
9-bit UART
Description
9-bit UART
8-bit UART
Description
th
th
data bit received. In Mode 1, SM20 is 0, RB80
data bit received. In Mode B, if SM21 is 0,
SM0
0
0
1
1
variable
variable
Baud Rate
SM1
0
1
0
1
Rev 2