71M6533 Maxim, 71M6533 Datasheet - Page 53

• Manufacturer Part Number: 71M6533
• Description: The Teridian™ 71M6533 and 71M6534 are third-generation polyphase metering systems-on-chips (SoCs) with a 10MHz 8051-compatible MPU core, low-power RTC, flash, and LCD driver
• Manufacturer: Maxim

SFR locations, i.e. the control registers internal to the 71M653x MPU, are not accessible via the SPI port.
In cases where these registers have to be accessed, for example to control DIO pins, a protocol that uses
the MPU has to be used for read and write operations involving the SFRs.
1.5.12 Hardware Watchdog Timer
An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6533/71M6534. It
uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every
Figure 17: Functions Defined by V1
Asserting ICE_E will also deactivate the WDT. This is the only method that will work in BROWNOUT mode.
In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The watchdog timer
is also reset when the internal signal WAKE=0 (see Section
Rev 2
V3P3 - 10mV
SERIAL READ
SERIAL WRITE
(From 653X)
(From 653X)
(From Host)
(From Host)
400mV
V3P3 -
VBIAS
V3P3
0V
PSDO
PSDO
PCSZ
PSCK
PCSZ
PSCK
PSDI
PSDI
V1
x
x
C7
C7
operation,
Figure 16: SPI Slave Port: Typical Read and Write Operations
0
0
enabled
Normal
Battery
WDT dis-
modes
WDT
abled
C6
C6
8 bit CMD
8 bit CMD
C5
C5
1.5 seconds. When not refreshed on time, the WDT overflows and the
part is reset as if the RESET pin were pulled high, except that the I/O
RAM bits will be in the same state as after a wake-up from SLEEP or LCD
modes (see the I/O RAM description in
states after RESET and wake-up). 4100 oscillator cycles (or 125 ms) after
the WDT overflow, the MPU will be launched from program address
0x0000.
A status bit, WD_OVF, is set when the WDT overflow occurs. This bit is
preserved in LCD mode (not in SLEEP mode) and can be read by the
MPU when WAKE rises to determine if the part is initializing after a WDT
overflow event or after a power-up. After it is read, the MPU firmware
must clear WD_OVF. The WD_OVF bit is also cleared by the RESET pin.
There is no internal digital state that deactivates the WDT. The WDT can
be disabled by tying the V1 pin to V3P3 (see
also deactivates V1 power fault detection. Since there is no method in
firmware to disable the crystal oscillator or the WDT, it is guaranteed that
whatever state the part might find itself in, upon watchdog overflow, the
part will be reset to a known state.
HI Z
C0
C0
7
7
A15
A15
8
8
A14
A14
16 bit Address
16 bit Address
A1
A1
HI Z
A0
A0
23
23
D7
D7
24
24
2.5 Wake Up
x
D6
D6
DATA[ADDR]
DATA[ADDR]
Section 5.2
D1
D1
Behavior).
31
31
D0
D0
Figure
D7
D7
32
32
Extended Read . . .
Extended Write . . .
for a list of I/O RAM bit
17). Of course, this
DATA[ADDR+1]
D6
DATA[ADDR+1]
D6
D1
D1
D0
D0
39
39
x
53