TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 144
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMP93xy20FG
Manufacturer Part Number
TMP93xy20FG
Description
Manufacturer
Toshiba
Datasheet
1.TMP93XY20FG.pdf
(264 pages)
Specifications of TMP93xy20FG
Package
LQFP144
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
M/P
Rom Combinations
64
Ram Combinations
2
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
4
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
-
Dual Clock
Y
Number Of I/o Ports
88
Power Supply Voltage(v)
4.5 to 5.5
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SC0MOD
(0052H)
Bit symbol
Read/Write
After reset
Function
Transfer
data bit8
Figure 3.9.2 Serial Mode Control Register (Channel 0, SC0MOD)
Undefined
TB8
7
0: CTS
1: CTS
Hand
shake
disable
enable
CTSE
6
0
0: Receive
1: Receive
Receiving
function
disable
enable
RXE
5
0
93CS20-142
0: Disable
1: Enable
Wakeup
function
WU
4
0
R/W
00: I/O interface mode
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
Serial transmission
mode
Note: The clock selection for the I/O interface
SM1
Serial transmission clock source (UART)
Serial transmission mode
Wakeup function
Receiving function
Handshake function (
Transmission data bit8
8-bit UART mode
(Parity)
9-bit UART mode
00
01
10
11
00
01
10
11
3
0
0
1
0
1
0
1
mode is controlled by the serial control
register (SC0CR).
I/O interface mode
UART mode
Timer 0 match detect signal
Baud rate generator
Internal clock φ1
External clock (SCLK0 input)
Interrupt when data
is received
Interrupt only when
RB8 = 1
Receive disable
Receive enable
Disable (Always transferable)
Enable
9-bit UART
SM0
2
0
Stores transmission parity
bit
Stores transmission data
bit8
CTS
7-bit length
8-bit length
9-bit length
00: TO0 trigger
01: Baud rate generator
10: Internal clock φ1
11: External clock
Serial transmission clock
(UART)
pin) enable
SC1
(SCLK0 input)
1
0
TMP93CS20
Other mode
Don’t care
2004-02-10
SC0
0
0
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