TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 51

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

(4) Notes
independently of each other. Therefore, if the instruction used to clear the interrupt
request flag of an interrupt is fetched before the interrupt is generated, it is possible
that the CPU might accept the interrupt and execute the fetched instruction to clear
the interrupt request flag while reading the interrupt vector. If so, the CPU would start
the interrupt processing from the address “FFFF28H”.
comes after the DI instruction. In the case of setting an interrupt enable again by EI
instruction after the execution of clearing instruction, execute EI instruction after
clearing instruction and following more than one instruction are executed. When EI
instruction is placed immediately after clearing instruction, an interrupt becomes
enable before interrupt request flags are cleared.
In the case of changing the value of the interrupt mask register<IFF2:0> by execution
of POP SR instruction, disable an interrupt by DI instruction before execution of POP
SR instruction.
The instruction execution unit and the bus interface unit of this CPU operate
To avoid this, make sure that the instruction used to clear the interrupt request flag
93CS20-49
TMP93CS20
2004-02-10