TMP93xy20FG Toshiba, TMP93xy20FG Datasheet - Page 183

• Manufacturer Part Number: TMP93xy20FG
• Manufacturer: Toshiba

Specifications of TMP93xy20FG

• Package: LQFP144
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): M/P
• Rom Combinations: 64
• Ram Combinations: 2
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 4
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: -
• Dual Clock: Y
• Number Of I/o Ports: 88
• Power Supply Voltage(v): 4.5 to 5.5

SCL pin
SDA pin
<PIN>
INTS2
interrupt request
Figure 3.10.13 Example of when <BC2:0> = 000, <ACK> = 1 (Transmitter mode)
(3) One-word data transfer
completed, and determine whether the mode is a master or slave.
a.
Test SBISR<MST> by the INTS2 interrupt process after a one-word data transfer is
When <MST> is 1 (Master mode)
receiver.
Implement the process to generate the stop condition (described later) and
terminate data transfer.
data is 8-bits, write it to the SBIDBR. When the next transmitted data is other
than 8 bits, set SBICR1<BC2:0>, set SBICR1<ACK> to 1, and write the
transmitted data to the SBIDBR. After writing the data, SBISR<PIN> becomes 1,
the serial clock pulse is generated for transferring a new one-word of data from
the SCL pin, and then the one-word data is transmitted. After the data is
transmitted, the INTS2 interrupt request occurs. <PIN> becomes 0 and the SCL
pin is set to the low level. If the data to be transferred is more than one word in
length, repeat the procedures from <LRB> test mentioned above.
Write to SBIDBR
Test SBISR<TRX> and determine whether the mode is a transmitter or
When <TRX> is 1 (Transmitter mode)
Check SBISR<LRB>. When <LRB> is 1, a receiver does not request data.
When <LRB> is 0, the receiver requests new data. When the next transmitted
D7
1
D6
2
D5
3
93CS20-181
D4
4
D3
5
D2
6
D1
7
D0
8
9
TMP93CS20
2004-02-10
Acknowledge
signal from a
receiver