STPCC4 STMicroelectronics, STPCC4 Datasheet - Page 81

• Manufacturer Part Number: STPCC4
• Description: STPC CONSUMER-II DATASHEET - X86 CORE PC COMPATIBLE INFORMATION APPLIANCE SYSTEM-ON-CHIP
• Manufacturer: STMicroelectronics

6.4.4. PCI INTERFACE
6.4.4.1. Introduction
In order to achieve a PCI interface which work at
clock
consideration has to be given to the timing of the
interface with all the various electrical and
physical constraints taken into consideration.
frequencies
up
Bridge
South
Bridge
North
Strap Options
delay
clock
to
HCLK PLL
Deskewer
MD[30:27]
33MHz,
MD[7:6]
Figure 6-23. Clock Scheme
Release 1.5 - January 29, 2002
1/2
1/3
1/4
MD[17,4]
MUX
careful
STPC
6.4.4.2. PCI Clocking Scheme
The PCI Clocking Scheme deserves a special
mention here. Basically the PCI clock (PCICLKO)
is generated on-chip from HCLK through a
programmable delay line and a clock divider. The
nominal frequency is 33MHz. This clock must be
looped to PCICLKI and goes to the internal South
Bridge through a deskewer. On the contrary, the
internal North Bridge is clocked by HCLK, putting
some additionnal constraints on T
PCICLKI
PCICLKO
HCLK
AD[31:0]
DESIGN GUIDELINES
0
T
T
and T
0
1
1
.
T
2
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