PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 168

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
12.4 Servicing Interrupts
12.5 Using the Performance Monitoring Features
PROPRIETARY AND CONFIDENTIAL
The TEMAP-84 will assert INTB to logic 0 when a condition which is configured
to produce an interrupt occurs. To find which condition caused this interrupt to
occur, the procedure outlined below should be followed:
1. Read the bits of the TEMAP-84 Master Interrupt Source register (0x0010) to
2. Read the bits of the second level Master Interrupt Source register to identify
3. Service the interrupt by reading the register containing the interrupt status bit
4. If the INTB pin is still logic 0, then there are still interrupts to be serviced.
The counters in the DS3 PMON block has been sized as not to saturate if polled
every second. The T1/E1 PMON event counters are of sufficient length so that
the probability of counter saturation over a one second interval is very small (less
than 0.001%).
An accumulation interval is initiated by writing to one of the PMON event counter
register addresses or by writing to the Global PMON Update register. After
initiating an accumulation interval, 3.5 recovered clock periods (RCLK for the
DS3 PMON) must be allowed to elapse to permit the PMON counter values to be
properly transferred before the PMON registers may be read.
The odds of any one of the T1/E1 counters saturating during a one second
sampling interval go up as the bit error rate (BER) increases. At some point, the
probability of counter saturation reaches 50%. This point varies, depending
upon the framing format and the type of event being counted. The BER at which
the probability of counter saturation reaches 50% is shown for various counters
in Table 18 for E1 mode, and in Table 19 for T1 mode.
identify which of the 14 interrupt registers (0x0011-0x001E) needs to be read
to identify the interrupt. For example, a logic one read in the DS3E3INT
register bit indicates that an interrupt identified in one of the three Master
Interrupt Source DS3/E3 registers produced the interrupt.
the interrupt source.
that is asserted.
Otherwise, all interrupts have been serviced. Wait for the next assertion of
INTB
Count registers respectively. The path maintenance datalink signal is
extracted by theDS3 RDLC HDLC receiver (if enabled).
ISSUE 1
156
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PM5366 TEMAP-84