PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 180

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
12.8 T1/E1 Loopback Modes
PROPRIETARY AND CONFIDENTIAL
the processing required at each point is described in the following paragraphs.
The actual interrupt signal, INTB, is active low and will be the inverse of the INT
signal shown in Figure 19. Also in this example, the programmable fill level set
point is set at 8 bytes by writing this value into the INTC[6:0] bits of the RDLC
Interrupt Control register.
At points 1 and 5 the first flag after all ones or abort is detected. A dummy byte
is written in the FIFO, FE goes low, and an interrupt goes active. When the
interrupt is detected by the processor it reads the dummy byte, the FIFO
becomes empty, and the interrupt is removed. The LINK ACTIVE (LA) software
flag is set to logic 1.
At points 2 and 6 the last byte of a packet is detected and interrupt goes high.
When the interrupt is detected by the processor, it reads the data and status
registers until the FIFO becomes empty. The interrupt is removed as soon as
the RDLC Status register is read, since the FIFO fill level of 8 bytes has not been
exceeded. It is possible to store many packets in the FIFO and empty the FIFO
when the FIFO fill level is exceeded. In either case the processor should use
this interrupt to count the number of packets written into the FIFO. The packet
count or a software time-out can be used as a signal to empty the FIFO.
At point 3 the FIFO fill level of 8 bytes is exceeded and interrupt goes high.
When the interrupt is detected by the processor it must read the data and status
registers until the FIFO becomes empty and the interrupt is removed.
At points 4 or 7 an abort character is detected, a dummy byte is written into the
FIFO, and interrupt goes high. When the interrupt is detected by the processor it
must read the data and status registers until the FIFO becomes empty and the
interrupt is removed. The LINK ACTIVE software flag is cleared.
The TEMAP-84 provides two loopback modes for T1/E1 links to aid in network
and system diagnostics. The internal T1/E1 line loopback can be initiated at any
time via the µP interface, but is usually initiated once an inband loopback
activate code is detected. The system Diagnostic Digital loopback can be
initiated at any time by the system via the µP interface to check the path of
system data through the framer.
T1/E1 Line Loopback
T1/E1 Line loopback is initiated by setting the LLOOP bit to a 1 through the TJAT
Indirect Channel Data register. When in line loopback mode, the appropriate
tributary in the TEMAP-84 is configured to internally connect the jitter-attenuated
ISSUE 1
168
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
AND M13 MULTIPLEXER
PM5366 TEMAP-84