PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 221

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
PROPRIETARY AND CONFIDENTIAL
TFPO/TMFPO[x]
TFPI/TMFPI[x]
TDATI[x]
TICLK[x]
Figure 43
Figure 44
The DS3/E3 Framer Only Mode Receive Output Stream diagram (Figure 43)
shows the format of the outputs RDATO, RFPO/RMFPO, RSCLK ROVRHD
when the OPMODE_SPEx[2:0] bits are set to “DS3/E3 Framer Only mode” in the
SPE Configuration registers. Figure 43 shows the data streams when the
TEMAP-84 is configured for the DS3 receive format. If the RXMFPO bit in the
DS3 and E3 Master Unchannelized Interface Options register is logic 0, RFPO is
valid and will pulse high for one RSCLK cycle on first bit of each M-subframe
with alignment to the RDATO data stream. If the RXMFPO register bit is a logic
1 (as shown Figure 43), RMFPO is valid and will pulse high on the X1 bit of the
RDATO data output stream. ROVRHD will be high for every overhead bit
position on the RDATO data stream. Figure 44 shows the output data stream
with RGAPCLK in place of RSCLK when the RXGAPEN bit in the DS3 and E3
Master Unchannelized Interface Options register set to logic 1. RGAPCLK
remains high during the overhead bit positions.
Figure 45
RFPO /RMFPO [x]
RGAPCLK[x]
RDATO[x]
RO VRHD[x]
RDATO [x]
RSCLK[x]
bit 1529
bit 1530
INFO 82
- Framer Mode DS3 Receive Output Stream
- Framer Mode DS3 Receive Output Stream with RGAPCLK
- Framer Mode G.751 E3 Transmit Input Stream
INFO 82
bit 1531
IN FO 83
bit 1532
IN FO 83
INFO 84
bit 1533
INFO 84
ISSUE 1
bit 1534
F4
bit 1535
INFO 82
bit 1536
INFO 82
INFO 83
INFO 83
1
209
INFO 84
1
INFO 84
1
X1
INFO 1
1
INFO 1
INFO 2
0
INFO 2
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
1
INFO 84
0
X2
0
INFO 1
INFO 1
0
INFO 2
INFO 2
AND M13 MULTIPLEXER
PM5366 TEMAP-84
0
IN FO 3
INFO 3
R A I
N at
INFO 82
INFO 82
bit13
INFO 83
INFO 83
INFO 84
INFO 84