PM5366-PI PMC-Sierra, Inc., PM5366-PI Datasheet - Page 85

• Manufacturer Part Number: PM5366-PI
• Description: HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER AND M13 MULTIPLEXER
• Manufacturer: PMC-Sierra, Inc.

PRELIMINARY
DATASHEET
PMC-2010672
9.5 T1/E1 Performance Data Accumulation
9.6 T1/E1 HDLC Receiver
PROPRIETARY AND CONFIDENTIAL
CRC error events, Frame Synchronization bit error events, and Out Of Frame
events, or optionally, Change of Frame Alignment (COFA) events are
accumulated with saturating counters over consecutive intervals as defined by
the period of the supplied transfer clock signal (typically 1 second). When the
transfer clock signal is applied, the counter values are transferred into holding
registers and resets the counters to begin accumulating events for the interval.
The counters are reset in such a manner that error events occurring during the
reset are not missed. If the holding registers are not read between successive
transfer clocks, the OVR context bit is asserted to indicate data loss.
A bit error event (BEE) is defined as an F-bit error for SF and SLC96 framing
format or a CRC-6 error for ESF framing format. A framing bit error (FER) is
defined as an F
format.
Generation of the transfer clock within the TEMAP-84 chip is generated precisely
once per second (i.e. 19440000 SREFCLK cycles) if the AUTOUPDATE bit of
the T1/E1 Framer Configuration and Status register is logic 1 or by writing to the
Global PMON Update register with the FRMR bit set.
The HDLC Receiver is a microprocessor peripheral used to receive HDLC
frames on the 4 kHz ESF facility data link or the E1 Sa-bit data link. A data link
can also be extracted from any sub-set of bits within a single DS0.
The HDLC Receiver detects the change from flag characters to the first byte of
data, removes stuffed zeros on the incoming data stream, receives packet data,
and calculates the CRC-CCITT frame check sequence (FCS).
Received data is placed into a 128-byte FIFO buffer. An interrupt is generated
when a programmable number of bytes are stored in the FIFO buffer. Other
sources of interrupt are detection of the terminating flag sequence, abort
sequence, or FIFO buffer overrun.
The RHDL Indirect Channel Data Registers contain bits which indicate the
overrun or empty FIFO status, the interrupt status, and the occurrence end of
message bytes written into the FIFO. The RHDL Indirect Channel Data
Registers also indicates the abort, flag, and end of message status of the data
just read from the FIFO. On end of message, the RHDL Indirect Channel Data
Registers indicates the FCS status and if the packet contained a non-integer
number of bytes.
s
or F
t
ISSUE 1
error for SF and SLC96 and an F
73
HIGH DENSITY 84/63 CHANNEL VT/TU MAPPER
e
error for ESF framing
AND M13 MULTIPLEXER
PM5366 TEMAP-84