ATA6613 ATMEL Corporation, ATA6613 Datasheet - Page 125

• Manufacturer Part Number: ATA6613
• Description: Ata6613
• Manufacturer: ATMEL Corporation

6.12.8
6.12.8.1
9111C–AUTO–02/08
8-bit Timer/Counter Register Description
Timer/Counter Control Register A – TCCR0A
Table 6-44.
Table 6-45
mode.
Table 6-45.
Note:
• Bits 7:6 – COM0A1:0: Compare Match Output A Mode
Initial Value
Read/Write
COM0A1
COM0A1
These bits control the Output Compare pin (OC0A) behavior. If one or both of the
COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OC0A pin must be set in order to enable the output driver.
When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM02:0 bit setting.
bits are set to a normal or CTC mode (non-PWM).
Bit
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See
for more details.
shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
COM0A1 COM0A0 COM0B1 COM0B0
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
R/W
COM0A0
COM0A0
7
0
0
1
0
1
0
1
0
1
R/W
Table 6-44
6
0
Normal port operation, OC0A disconnected.
Toggle OC0A on Compare Match
Clear OC0A on Compare Match
Set OC0A on Compare Match
Description
Normal port operation, OC0A disconnected.
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
Clear OC0A on Compare Match, set OC0A at TOP
Set OC0A on Compare Match, clear OC0A at TOP
Description
R/W
5
0
shows the COM0A1:0 bit functionality when the WGM02:0
R/W
4
0
R
3
–
0
(1)
ATA6612/ATA6613
R
2
–
0
“Fast PWM Mode” on page 120
WGM01
R/W
1
0
WGM00
R/W
0
0
TCCR0A
125